Heat has become one of the most critical issues in computer and semiconductor design: The ever increasing number of transistors in computer chips requires more efficient cooling approaches for the hot spots which are generated as a result of the operation of the transistors. Researchers have now demonstrated a microfluidic technique of using thermally conductive and magnetic nanoparticles that can form low-dimensional fins in the vicinity of hot spots. This work is the first ever report on using nanoparticles for making nanofins on demand in microfluidics.
Over the past few years, we have seen an explosion of interest in electronic devices based on paper or textile components. These substrates are attractive because they can impart flexibility and low- cost manufacturing to devices such as transistors, circuits, light-emitting diodes, and batteries. They also can be folded. Researchers now have have shown that paper-folding concepts can be applied to Li-ion batteries in order to realize a device with higher areal energy densities.
The idea of building bio-inspired cognitive adaptive solid-state devices has been around for decades. It forms the basis for synaptic electronics, a field of research that aims to build artificial synaptic devices to emulate the computation performed by biological synapses. Synapses dominate the architecture of the brain and are responsible for massive parallelism, structural plasticity, and robustness of the brain. They are also crucial to biological computations that underlie perception and learning. Therefore, a compact nanoelectronic device emulating the functions and plasticity of biological synapses will be the most important building block of brain-inspired computational systems. Now, a new review looks at the recent progress of synaptic electronics.
A team of researchers in Germany and the U.S. demonstrates that it is possible to operate extremely compact optical circuits on the nanoscale, a size scale that makes it compatible and potentially competitive with state-of-the-art electronic microchips, while substantially reducing the limiting factor of heating loss and while strongly increasing the efficiency to funnel infrared laser light into these circuits with a novel design of optical nanoantennas.
Notwithstanding the red-hot research area of flexible electronics, today's state-of-the-art electronic devices rely on rigid and brittle mono-crystalline silicon based transistors which are unmatched with regard to low-cost production, high-performance computing, and ultra-low power consumption. Researchers have now developed a low-cost generic batch process using a state-of-the-art CMOS process to transform conventional silicon electronics into flexible and transparent electronics while retaining its high-performance, ultra-large-scale-integration density and cost.
In contrast to flexible electronics, which rely on bendable substrates, truly foldable electronics require a foldable substrate with a very stable conductor that can withstand folding, i.e. an edge in the substrate at the point of the fold, which develops creases, and the deformation remains even after unfolding. That means that, in addition to a foldable substrate like paper, the conductor that is deposited on this substrate also needs to be foldable. Researchers have now demonstrated a fabrication process for foldable graphene circuits based on paper substrates.
Graphene has a unique combination of properties that is ideal for next-generation electronics, including mechanical flexibility, high electrical conductivity, and chemical stability. Combine this with inkjet printing, already extensively demonstrated with conductive metal nanoparticle ink, and you get an inexpensive and scalable path for exploiting these properties in real-world technologies. Although liquid-phase graphene dispersions have been demonstrated, researchers are still struggling with sophisticated inkjet printing technologies that allow efficient and reliable mass production of high-quality graphene patterns for practical applications. Recent work has addressed these issues and proposes an approach to overcome these problems.
Semiconductor fabs are large, complex industrial sites with costs for a single facility approaching $10B. In this article we discuss the possibility of putting the entire functionality of such a fab onto a single silicon chip. We demonstrate a path forward where, for certain applications, especially at the nanometer scale, one might consider using a single chip approach for building devices, both integrated circuits and nano-electromechanical systems. Such methods could mean shorter device development and fabrication times with a significant potential for cost savings.