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Posted: April 27, 2009
Cypress Semiconductor Unveils Market's First SRAM on 65-nm Process Technology
(Nanowerk News) Cypress Semiconductor Corp. , an industry leader in SRAMs, today announced it is sampling the industry’s first Quad Data Rate™ (QDR™) and Double Data Rate (DDR) SRAM devices on 65-nm linewidth. The new 72-Mbit QDRII, QDRII+, DDRII and DDRII+ memories leverage process technology developed with foundry partner UMC. The new SRAMs feature the market’s fastest available clock speed of 550 MHz and a total data rate of 80 Gbps in a 36-bit I/O width QDRII+ device, using half the power of 90-nm SRAMs. They are ideal for networking applications, including Internet core and edge routers, fixed and modular Ethernet switches, 3G base stations and secure routers, and also enhance the performance of medical imaging and military signal processing systems. The devices are pin compatible with 90-nm SRAMs, enabling networking customers to increase performance and port density while maintaining the same board layout.
Compared with their 90-nm predecessors, the 65-nm QDR and DDR SRAMs lower input and output capacitance by 60 percent. The QDRII+ and DDRII+ devices have On-Die Termination (ODT), which improves signal integrity, reduces system cost and saves board space by eliminating external termination resistors. The 65-nm devices use a Phase Locked Loop (PLL) instead of a Delay Locked Loop (DLL), which enables a 35 percent wider data valid window to reduce development time and cost for the customer.
“We continue to expand our Synchronous SRAM portfolio to broaden our target markets and grow market share,” said Dana Nazarian, Executive Vice President of the Memory and Imaging Division at Cypress. “Cypress is committed to supporting the SRAM market long-term and building on our leadership position.”
The 65-nm QDRII, QDRII+, DDRII and DDRII+ SRAMs are all currently sampling, with production expected in Q3 2009. Each device is available in multiple configurations based on I/O width (x18 or x36), burst length (B4 or B2) and latency (1.5, 2.0 or 2.5). The 65-nm 72-Mbit SRAMs are available in a standard 165-pin Fine-pitch Ball Grid Array (FBGA) package and are pin-compatible with existing 90-nm QDR and DDR devices for easy migration.