Posted: April 29, 2009

(Nanowerk News) Takumi Technology Corporation, a leading developer in high-performance layout optimization software for equipment and integrated circuit (IC) manufacturers, announced today it has been issued a patent by the United States Patent and Trademark Office for its methods in system for simplifying layout processing. The patent, #7,487,490, covers technology in layout processing to enhance manufacturability of integrated circuits layouts for 65 nm processes and below.
As the gap between design and manufacturability in sub-wavelength technology widens, IC manufacturers are turning to optical resolution enhancement techniques such as optical proximity corrections in their design and manufacturing schema to produce features sizes of 65 nm or smaller. As the feature size decreases, distortion in the pattern transfer process becomes more severe forcing the design shapes to be modified such that the desired images can be printed on a wafer. These modifications account for the limitations in the optical lithography process as well as mask fabrication limitations and resist limitations.
Optical proximity correction on real design layouts is often handicapped by the existence of nuisance jogs that may be due to design rule or post-design processing. The existence of jogs or other imperfections increase the complexity of the original layout resulting in dramatic increase in the volume of data, which subsequently complicates layout processing. Jogs also force dissections at less-than-optimal locations, or simply miss dissection and correction when a jog is too small.
This patent describes a simplified layout processing system that overcomes these limitations. "This patent, in conjunction with five other patents previously granted to Takumi Technology in the areas of photolithographic mask correction and design for manufacturability gives us a strong technology foundation for our business," said Akifumi Goto, CEO and president of Takumi Technology.
Source: Takumi Technology (press release)