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Posted: May 11, 2009
Rudolph Announces New MetaPULSE-G Copper Film Metrology System
(Nanowerk News) Rudolph Technologies, Inc., a worldwide leader in process characterization solutions for the semiconductor manufacturing industry, announced today the availability of its new MetaPULSEŽ-G thin film measurement tool optimized specifically for copper damascene processes at 45nm through 22nm technology nodes and copper via fill in new 3D IC applications. Copper thickness and overburden measurements are critical in optimizing the CMP process that follows deposition during through-silicon via (TSV) manufacturing. The new tool measures 60-80 product wafers per hour with gauge-capable precision and reduced cost of ownership. Rudolph is accepting orders now with initial shipments planned for the fourth quarter of 2009.
"Our MetaPULSE line is the industry standard for thickness measurements on opaque films," commented Jack Kurdock, Rudolph's vice president and general manager of the Metrology Business Unit. "The MetaPULSE-G reinforces that position with superior performance on the copper films that are critical in today's advanced device technologies and new TSV processes. The MetaPULSE has a ten micron spot size that is fully capable of measuring films within advanced test sites and in the active die on product wafers at throughputs that can support high-volume production. Most important, and unlike optical and x-ray techniques, the MetaPULSE measures film thickness using a time-resolved acoustic signal that can be used in active die in the absence of special underlying test pads."
The high-reliability, green wavelength ultrafast laser used in the MetaPULSE-G is optimized for copper applications, delivering higher signal-to-noise ratios and measurement repeatability better than 0.3 percent at throughputs of 60-80 WPH. The system's 10um X 10um spot size is small enough to assure measurement capability on product wafers in 30x30um or smaller test sites.
A TSV 3D package (3D IC) contains two or more chips stacked vertically, with vias through the silicon substrates replacing edge wiring to create an electrical connection between the circuit elements on each chip. TSV technology provides a dramatic increase in the functionality of the device in a very small footprint. Multiple technologies are being explored to form vias during the wafer fabrication process (front-end) and the IC packaging and assembly stage (back-end). Metrology and inspection of the TSVs are critical for ensuring the performance of the 3D ICs and the profitability of the overall manufacturing process.