The initial goals of the consortium were to bring to market individual unit processes that can be quickly adopted into a volume production environment, and establish a basic understanding of the interactive relationship between process steps, all for a low overall Cost of Ownership (CoO) for 3D chip stacking.
The consortium originally identified a CoO target of $200usd per wafer for a fully processed die-to-wafer 3D stack on 300mm wafers. "Improvements of equipment efficiency, simplified process flow and reduced material expenses have been instrumental in lowering cost," said Paul Siblerud, EMC3D project director. "Today, fabs running iTSV can produce 3D-TSV devices at a total CoO of less than $150usd per wafer. Improved synchronization between the unit processes along with aggressive cost saving designs have been very successful at exceeding the consortium's original cost goals."
Sesh Ramaswami of Applied Materials said, "It has become clear that the larger diameter via-last pTSV used in DRAM, interposers and CIS devices have significantly different challenges than the smaller diameter high aspect ratio via-first iTSV structures. From etch and metallization, film stress management thru CMP and wafer bonding through debonding, these challenges require an integrated approach that EMC3D will focus on during this program extension."
"We are expanding our goal to include reliability improvements of both via-first (iTSV™) and via-last (pTSV™) processes," said Bioh Kim of EV Group. "Extending the roadmap to include a significantly reduced CoO to under $120usd per wafer will be a challenge, but one each member looks forward to working on."
EMC3D (Semiconductor 3D Equipment and Materials Consortium) was created in September 2006 to develop and market wafer level 3D chip stacking technology by demonstrating a cost-effective, manufacturable, stackable TSV interconnection process for IC and MEMS/Sensor packaging.
*3D: three dimensional; MEMS: microelectromechanical systems; iTSV is interconnect Through-Silicon-Via; and pTSV is packaging Through-Silicon-Via or Via-First and Via-Last respectively.