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Posted: July 27, 2009
STMicroelectronics Adopts Encounter Signoff Solutions for Designs From 65 to 32 Nanometers
(Nanowerk News) Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced that STMicroelectronics, a global leader in integrated circuits for communications, consumer, computer, automotive and industrial applications, has adopted the complete Cadence integrated signoff solutions consisting of QRC Extraction and Encounter Timing System, for 65- and 45-nanometer design, and is actively qualifying the system for 32 nanometer process technologies. The Cadence signoff suite delivers a seamless integration of all the analysis components in a single cockpit, and with the complete Encounter implementation design flow. This approach to integrated signoff provides fast convergence, predictable design closure, and completely scalable multi-CPU backplane to enable overall cycle time reduction.
"At 65- to 45-nanometer process nodes, signoff solutions need to deliver accurate silicon predictability, high performance and integration with digital implementation flows to meet our time-to-market," said Philippe Magarshack, group vice president and general manager, Central CAD and Design Solutions, Technology R&D, STMicroelectronics. "Cadence's signoff combination of QRC Extraction and Encounter Timing solution demonstrated excellent design convergence which met our stringent accuracy specifications for our complex designs. This gave us the confidence to further extend qualification to our most advanced 32-nanometer projects."
The 65- and 45-nm flow qualification included rigorous evaluations involving multiple criteria and various design styles.
"Adopting Cadence's QRC Extraction and Encounter Timing System for our design teams and customers was the natural choice for ST given our successes with the tool at advanced nodes," said Thierry Bauchon, R&D Director, Home Entertainment and Displays Group, STMicroelectronics. "The Cadence integrated signoff suite delivers significant advantages in runtime and accuracy, and facilitates a seamless design flow through integration with Encounter Digital Implementation System."
"STMicroelectronics and Cadence have worked closely and successfully together to solve the industry's most complex challenges over the years. Our vision to integrate production-proven signoff technologies directly with our design implementation solution is an industry first and a great technology advancement to address design closure challenges with advanced process nodes," said Dr. Chi-Ping Hsu, senior vice president of Implementation Products at Cadence. "We are pleased that the Cadence integrated signoff technology delivered superior results for ST's most advanced technologies and designs, and we look forward to continuing our close partnership to deliver new breakthroughs for STMicroelectronics and Cadence."
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.