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Posted: August 11, 2009
Cove Announces New Method to Form Ultra-Thin Device Wafers
(Nanowerk News) Cove Technology, Inc. (CTI) announced a new method for forming ultra-thin device wafers which is cheaper and more uniform than conventional methods using SOI or back grinding techniques. The patent pending ThinMOS™ technology is a fully integrated process flow which only adds a few extra processing steps to conventional CMOS fabrication, and provides extraordinary uniformity across the entire substrate.
Two key applications for ThinMOS include thinning substrates for backside illuminated imagers and die stacking. The current trend for CMOS image sensors to utilize back-side illumination to maximize the fill factor and to allow significant pixel shrinkage has been delayed due to the cost and difficulty to make substrate layers thinner than 5 um with adequate uniformity across an entire 300mm substrate. Additionally, stacking homogeneous memory chips in a single package requires significant thinning of the device substrates, particularly when Wafer Level Packaging (WLP) technologies such as through-silicon via (TSV) structures are incorporated. As TSV structures become even smaller and allow 3D interconnections with thinned, stacked device substrates, it becomes even more critical to have a cost-effective, fully integrated thinning process.
“ThinMOS provides the solution to form ultra-thin device substrates for a variety of applications. Reducing package size and increasing device performance are critical to the future of the semiconductor industry. Back-side illuminated image sensors and 3D interconnect structures would benefit immediately from the utilization of this fully integrated process”, according to Mark E. Tuttle, the President of CTI, and the inventor of this new approach.
For additional information regarding ThinMOS, potential licensees and investors may contact Mark E. Tuttle at [email protected] This announcement is not an offer to buy or sell securities.
CTI was founded by Mr. Tuttle in 2007 to develop new technologies and provide consulting in the areas of semiconductors, wafer level packaging, solar, and bioelectronics. Mr. Tuttle has over 200 issued patents in many different technology areas and recently published the chapter, ‘3D Memory Applications’, in the Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, edited by Garrou et al., 2008, Wiley-VCH.