New transistor noise model improves prediction accuracy, supports continued device scaling
(Nanowerk News) Researchers from SEMATECH’s Front End Processes (FEP) program have developed a comprehensive transistor noise model capable of extracting defect characteristics from low frequency noise data in advanced gate stack transistors using both conventional and novel dielectrics. The proposed model is a key step towards identifying and minimizing defects to support aggressive device scaling. SEMATECH’s results were presented at the IEEE Integrated Reliability Workshop (IRW) on Thursday, October 22, in Lake Tahoe, CA.
Low frequency noise — random fluctuations in device current — is a growing concern in the performance of integrated CMOS circuits, particularly as the industry continues relentless device scaling and new materials are introduced. The root of the “noise” is electrons jumping from the substrate up into a defect in the dielectric and back. The conventional model for low frequency noise, which was acceptable up to recent technology nodes, does not work well now, as pointed out by NIST researchers earlier this year (ref=IEEE Spectrum Aug 2009 Vol 46, pg 16) - the model prediction for carrier capture rates is off by 1000x or more.
To address this issue, SEMATECH’s FEP researchers have employed the concept of 'lattice relaxation' around a defect; when the defect traps a charge (electron), the neighboring nuclei “feel” its Coulomb potential and shift their position slightly to accommodate this additional force – that is, they ‘relax’ around the defect. This relaxation requires a finite amount of energy, amounting to a barrier which slows down the rate of capture.
The use of noise characterization is of particular interest to the reliability community, where it has become a valuable diagnostic technique in the development of semiconductor materials and devices. “To optimize noise performance in various applications, we need to be able to accurately simulate the processes responsible for noise,” said Gennadi Bersuker, project manager of electrical characterization and reliability at SEMATECH. “With the proposed model, the reliability community now has a means of identifying the atomic structure of the defects, allowing feedback to process and integration groups to facilitate reduction and elimination of the defects.”
Michael Shur, the Patricia W. and C. Sheldon Professor of Solid State Electronics at Rensselaer Polytechnic Institute, said that the mechanism of structural relaxation of the traps in MOSFETs discovered by the SEMATECH group is the key to understanding and minimizing noise and, hence, is of extreme importance for scaling advanced device structures. “The SEMATECH work explains several orders of magnitude difference between older, so-called, tunneling models and the noise measured in advanced CMOS with ultrathin oxide layers,” said Prof. Shur.
In collaboration with member companies, universities, national labs, and supplier partners, the core technical teams of SEMATECH’s FEP program are consistently developing innovative techniques for extending high-k dielectrics, metal gates, high mobility channels, and advanced memory technologies.
About SEMATECH
For over 20 years, SEMATECH® has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Today, we continue accelerating the next technology revolution with our nanoelectronics and emerging technology partners.
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