The latest news from academia, regulators
research labs and other things of interest
Posted: December 7, 2009
First-Ever Device Highlights the Potential of Self-Assembling Patterning for Transistors Smaller Than 22 Nanometers
(Nanowerk News) Semiconductor Research Corporation (SRC), the world's leading university-research consortium for semiconductors and related technologies, and researchers from Stanford University and Taiwan Semiconductor Manufacturing Company (TSMC) today announced they have developed the industry’s first top-gated field effect transistor (FETs) and CMOS inverters featuring 20 nanometer (nm) contact holes using diblock copolymer lithography. This advance could help extend the manufacturability of semiconductors beyond conventional lithography methods, with the potential for enabling electronics makers to meet the demand for smaller, faster and cheaper devices.
The ever-shrinking lithography processes for semiconductors have produced dramatic size, speed and cost benefits for the electronics industry. However, the industry faces certain physical and economic constraints as it moves to smaller transistor scales, or nodes. In particular, the industry has yet to find a manufacturing solution to patterning feature sizes beyond the 22nm node.
In recent years, researchers have begun to look at block copolymers, an organic material that is compatible with conventional semiconductor manufacturing processes, because a thin film of it, under the right conditions, can self-assemble into regular arrays of holes on the order of 20nm or smaller in diameter. This tiny, self-assembled swiss cheese of block copolymer can act as a stencil for creating electrical contacts to very small semiconductor devices.
Previous attempts at using block polymers have fallen short because the self-assembled holes were not aligned to existing electrical features on the semiconductor wafer. Now, the SRC-sponsored work by researchers from Stanford University and TSMC has produced the industry’s first functional devices and circuits that employ diblock copolymer patterning for sub-22nm CMOS technologies on a full wafer scale.
“We believe this development will help to bring self-assembly closer to broad application in the semiconductor industry and will help increase the use of nanotechnology for advancements in electronics for years to come,” said H.-S. Philip Wong, a professor of Electrical Engineering at Stanford University.
“Professor Wong’s work demonstrates that diblock copolymers, via directed self-assembly, can enable several key integration steps in the fabrication of nanoscale devices,” said Dan Herr, SRC director of Nanomanufacturing Sciences.
The research is expected to catalyze further innovations in the area of extensible nanomanufacturing and possibly be integrated into the manufacturing process in the next seven to 10 years.
More information about the research and results will be published in a paper entitled “Top-Gated FETs/Inverters with Diblock Copolymer Self-Assembled 20nm Contact Holes” and presented at IEEE’s 2009 International Electron Devices Meeting in Baltimore, Md., on December 9. The paper is co-authored by graduate student, Li-Wen Chang and H.-S. Philip Wong of Stanford University, and T.L. Lee, Clement H. Wann, and C.Y. Chang of TSMC.
Celebrating 27 years of collaborative research for the semiconductor industry, SRC defines industry needs, invests in and manages the research that gives its members a competitive advantage in the dynamic global marketplace. Awarded the National Medal of Technology, America’s highest recognition for contributions to technology, SRC expands the industry knowledge base and attracts premier students to help innovate and transfer semiconductor technology to the commercial industry.
Source: Semiconductor Research Corporation (press release)