| Posted: February 22, 2010 |
EU-funded research project launched to investigate on reliable terascale memory systems |
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(Nanowerk News) The European Commission has launched a joint FP7 Future Emerging Technology research project TRAMS aiming to investigate the impact of increasing variability and decreasing reliability of the components in future terascale memory systems and to create new design paradigms which can secure their reliable operation in future multicore processors and system on a chip applications.
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The TRAMS (Terascale Reliable Adaptive Memory Systems) project consortium includes Intel Corporation Iberia, the nanoelectronics research center imec, the University of Glasgow (UOG) and the Universitat Politècnica de Catalunya (UPC).
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The project targets transistors, circuits and systems near the end of the International Roadmap for Semiconductors (ITRS) and beyond. A starting point will be the Late CMOS technologies after the 16 nm technology generation including novel multigate device architectures and novel channel and gate stack materials expecting to reach important scaling challenges below 10 nm dimensions.
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Beyond-CMOS emerging technologies such as nanowire transistors, quantum devices, carbon nanotubes, graphene, or molecular electronics are expected to scale below 5 nm. Both the Late CMOS and the Beyond CMOS technologies hold the promise of a significant increase in device integration density complemented by an increase in system performance and functionality. However, a dramatic reduction in single device quality is also expected, complemented by an increase in variability, severe reduction of the signal to noise ratio, and severe reliability problems. Therefore, alternative circuit and system solutions need to be investigated to deliver reliable systems out of variable and unreliable components and keep harvesting the benefits fueled by technology scaling. In this project we focus on the memory system of terascale processors.
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Memory cells and, in general, system architectures for nanotechnologies (both late CMOS and emerging devices) need to address the variability and reliability problem. In order to build reliable nanosystems, the TRAMS project will apply a specific variability and reliability-aware analysis and design flow as well as a hierarchical tolerance design. The project will investigate novel solutions at circuit and architecture levels, which will be able to provide reliable memory systems out of unreliable nanodevices at a reasonable cost and design effort.
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