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Posted: June 22, 2010

Delivering the Industry's Lowest Power 28nm FPGAs

(Nanowerk News) Xilinx, Inc. has announced the industry's first FPGA series that slashes total power consumption by 50 percent and offers industry-leading capacity of up to 2 million logic cells on the only unified architecture that scales across low-cost to ultra high-end families. Xilinx(R) 7 series FPGAs further extend the range of applications programmable logic can address by breaking new ground in solving customer challenges for lower power and cost without compromising on higher capacity and increased performance. Implemented on 28-nanometer (nm) process technology optimized to deliver low power with high performance, the new families enable significant levels of productivity as skyrocketing development costs, complexity, and inflexibility of alternative ASIC and ASSP technology make FPGA platforms more relevant to an increasingly diverse community of designers.
The 28nm families extend Xilinx's Targeted Design Platform strategy introduced with the company's 40nm Virtex(R)-6 and 45nm Spartan(R)-6 FPGA families, now in volume production. The Targeted Design Platform strategy combines FPGAs, ISE(R) Design Suite software tools and IP, development kits, and targeted reference designs to enable customers to leverage their existing design investments and reduce their overall costs as they meet evolving market needs. In this new generation, Xilinx also takes a critical next step in its work to dramatically expand the ecosystem of available IP and designs that enable customers to focus on differentiation even as they transition to 28nm devices.
"The 7 series represents a new juncture for Xilinx, and the FPGA industry in general, as we bring our technology portfolio to new markets by putting a significant emphasis on lowering power consumption," said Xilinx President and CEO Moshe Gavrielov. "In addition to delivering what we and our customers expect from Moore's Law in terms of capacity and performance with each new generation, we continue our focus on opening programmable logic to a broader audience by delivering design platforms targeted toward the specific needs of new users and markets."
Delivering the Industry's Lowest Power 28nm FPGAs
The new FPGA families enable developers to implement programmable solutions in a range of systems that had previously only been achievable in ASSPs or ASICs, including portable ultrasound equipment consuming less than 2 watts and automobile infotainment systems driven by 12 volts, as well as low-cost LTE baseband and femtocell base stations.
Xilinx placed an intense focus on minimizing total power by adopting a unique HKMG (high-K metal gate) process optimized for low static power consumption (see "Xilinx Picks 28nm High-Performance, Low-Power Process to Accelerate Platforms for Driving the Programmable Imperative"). Working with its foundry partners, Xilinx helped define the new process to achieve FPGA performance requirements, while lowering static power consumption by 50 percent compared to the alternative 28nm high-performance process. Xilinx then applied innovative architectural enhancements to lower dynamic power consumption both for logic and I/O, while also introducing intelligent clock-gating technology with the release of ISE Design Suite 12. The result is an FPGA series that provides 50 percent lower total power consumption compared to Virtex-6 and Spartan-6 FPGAs and 30 percent lower than alternative 28nm FPGA device families.
The significantly lower power consumption not only enables FPGAs to target new applications, it also allows Xilinx to deliver the most usable performance in the 28nm generation of devices. This means designers can take full advantage of up to 4.7TMACS (trillion multiply accumulates per second) in DSP performance symmetric mode (2.37TMACS in non-symmetric mode) and 2 million logic cells at clock speeds of up to 600MHz, and achieve up to 2.4Tbps high-speed connectivity all while staying within their power budgets.
New Unified Architecture Enables Scalability and Increases Productivity
All 7 series FPGAs share a unified architecture that enables customers to easily scale their designs up or down in capability to reduce cost and power or increase performance and capability, thereby reducing their investment in developing and deploying products across low-cost and high-performance families. The architecture is derived from the widely successful Virtex-series-based architecture and has been designed to simplify reuse of current Virtex-6 and Spartan-6 FPGA designs. It is also supported by the proven EasyPath(TM) FPGA cost reduction solution that further improves productivity by enabling a guaranteed 35 percent cost reduction with no incremental conversion or engineering investment.
Customers who need the lower power or increased system performance and capacity provided in the new 7 series FPGAs can begin designs in Virtex-6 and Spartan-6 FPGAs with the confidence that they can move their designs when the time is right. This unified architecture is facilitated by Xilinx's adoption of the AMBA AXI interconnect standard enabling plug-and-play IP usage to help customers improve productivity and development costs.
"Integrating 6-LUT architecture and working with ARM on the AMBA specification for these devices supports IP reuse, portability, and predictability," said Andy Norton, CTO for Systems Architecture, Cloudshield Technologies, an SAIC company. "A unified architecture, new paradigm-changing processor-centric devices and hierarchical-based design flows in next-gen tools, will result in increased productivity, flexibility, system-on-chip capabilities and portability from previous generation architectures."
The devices use the same logic architecture, Block RAM, clocking technology, DSP slices, and SelectIO(TM) technology and build on previous generations of devices delivered by Xilinx's patented Virtex series ASMBL(TM) block architecture. This next generation ASMBL architecture provides unprecedented flexibility and scalability that enables customers to most effectively utilize the full range of logic densities.
Source: Xilinx (press release)
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