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Posted: September 2, 2010
GBP 2.5M Funding to Commercialize Breakthrough Carbon Nanotube Interconnection Process for Next-generation Semiconductors
(Nanowerk News) Surrey NanoSystems has secured second round funding of £2.5 million (~US$4.2m) from Octopus Ventures, IP Group, The University of Surrey and other investors. The capital will help to commercialize an innovative low-temperature growth process for carbon nanotubes, targeted for use as an interconnection technology in semiconductor devices. The innovation will help silicon integrated circuit manufacturers to overcome a critical problem that threatens the evolution to next-generation geometry sizes, speeds and power conservation.
Octopus Ventures, a specialist investor in early-stage and expanding companies provided £1.75m (~US$3m). Surrey NanoSystems' initial venture capital investor IP Group - through IP Venture Fund - together with The University of Surrey and other investors provided £0.75m (~US$1.3m).
"The semiconductor industry urgently needs a new interconnection technology. If you can solve the problem of growing precision carbon nanotubes at silicon-friendly temperatures - and we have - it opens up a massive potential market," says Ben Jensen, CTO of Surrey NanoSystems. "We expect to be the company that is able to offer a viable new interconnection process for high-volume semiconductor fabrication, one that really exploits the incredible performance properties of carbon nanotubes."
Manufacturers currently use copper to provide the vertical interconnections required for integrated circuit (IC) fabrication, but this material is running into technical difficulties as the geometry sizes of ICs shrink. Carbon nanotubes (CNTs) can be structured to act as extremely efficient conductors, but their adoption as a replacement for copper has been hindered by the fact that conventionally-grown CNTs require temperatures of around 700 degrees C, too high for semiconductor processing. In contrast, Surrey NanoSystems' fabrication system and process allows CNT structures to be grown at silicon-friendly processing temperatures of 350 C or less.
Surrey NanoSystems was established in 2006 as a spin-out from the University of Surrey's Advanced Technology Institute (ATI), with the help of individuals having a successful background in the design of thin-film deposition systems. ATI had developed pioneering intellectual property concerning the fabrication of CNTs at low temperature. This combination of know-how allowed the company to quickly develop an architectural platform called NanoGrowth. This equipment implements a unique process incorporating ATI's patented know-how, and several unique additional techniques, that deliver the conditions for the growth of precision CNTs at both the temperatures and densities needed for state-of-the-art CMOS ICs. The initial development effort was supported by first round funding from IP Group, who specialize in commercializing intellectual property originating from research-intensive institutions.
The initial focus of Surrey NanoSystems has been the provision of equipment to developers researching and prototyping CNTs to advance the performance and integration density of semiconductors and electronic devices. The company's focus is now optimizing its technology for the mass-volume manufacturing environment, by scaling the hardware and refining and scaling the materials processing technology.
The new funding will support this evolution, allowing Surrey NanoSystems to greatly extend its engineering and development capabilities with a new technology laboratory, several brand-new systems of its own design, and more staff. These resources will be used to scale the company's materials growth technology from its current 100 mm wafer size capability, to the 300 mm sizes used in commercial wafer fabrication plants. Surrey NanoSystems will also add an industry-standard SEMI interface to its process equipment, allowing it to be integrated easily onto standard wafer-processing cluster tools. Alongside this development work, Surrey NanoSystems is pursuing technology partnerships with both semiconductor manufacturers and volume cluster tool suppliers, to shorten the path to market for its technology.