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Posted: Aug 22, 2011

Electrodeposition moving to ever smaller dimensions

(Nanowerk News) To tackle future electrodeposition challenges, imec is doing research to understand all the physics involved, and to develop processing routes. As part of that effort, it has set up a collaboration with the lab of Prof. J. Deconinck at the VUB (Vrije Universiteit Brussels). The focus of the collaboration is to develop a simulation platform that can be used as a tool for exploring new electrodeposition strategies. By combining the expertise fields of experiments and simulations and their mutual validation, the project aims at yielding a simulation tool which captures the essential processes occurring at wafer level, and thus handle 'real case' situations. The project's results will be fed into the development work for both the 3D and advanced interconnect programs.
Schematic representation of electrodeposition on wafer level
Schematic representation of electrodeposition on wafer level. Electrical contacts are made at the wafer perimeter and deposition starts close to the electrodes, leading to a growth front progressing towards the wafer center. During deposition, the wafer contains different regions, such as a continuous copper layer (III), a region of growth nucleation (II), and a barrier layer only (I).
In semiconductor processing, the dimensions of the structures that are created and subsequently filled using electrodeposition can differ over many orders of magnitude. One example are TSVs (through-silicon vias), which are interconnects between the chips in a vertical 3D stack. These have dimensions in the range of microns (diameters of 210m and depths of 50100 m). For damascene-type structures, Cu interconnects are formed as contacts between various CMOS layers. The dimensions of these interconnects are smaller (in the range of < 20nm). In addition, scaling will continue for the foreseeable future. It is foreseen that traditional approaches, in which a Cu seed layer is deposited in a structure and electrodeposition is done on such a substrate, will, at some point, not be usable anymore.
Our R&D focuses on three work packages: (1) modeling the reaction mechanism of the components that are present in an electrodeposition bath by adjusting the reaction speed parameters and diffusion rates to match experimental results, (2) finding numerical solutions to cope with the surface modifications inside the structures during the deposition process, and (3) tackling the wafer scale Cu deposition. Recently, the project team has been extended with the lab of Prof. A.C. West (Columbia University, NY, USA), with whom we will be working on deposition front propagation, one of the essential features occurring on wafer level.
One of the electrodeposition strategies that are investigated is direct plating on a barrier material. This is a method that will allow downscaling the filling further than the classical approach. The electrodeposition of copper on any other barrier/seed material has drawn a large interest from the industry, and nucleation studies have been reported in literature for various materials. The nucleation process is controlled by various parameters, such as potential and current at which the Cu is plated, surface conditions of the substrate, electrolyte composition, various additives present in the bath, and the electrical resistivity of the substrate. Factors such as copper front propagation and terminal effects are to be taken into account. A numerical model has been set up by the team, aiming to understand the fundamentals underlying the (electro-)chemical deposition process. For a successful implementation on wafer scale, one needs to obtain a fast coverage of the entire surface and fill small features void-free, both of which are challenging to achieve in one-and-the same process.
Source: imec
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