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Posted: Oct 04, 2011

Analog Bits Uses Berkeley Design Automation to Deliver 100 Gbps 40nm PLL IP Silicon Success for SoC and Cloud Computing Applications

(Nanowerk News) Berkeley Design Automation, Inc., provider of the world's fastest nanometer circuit verification, today announced that Analog Bits, a leading provider of integrated clocking and interface IP, has adopted and achieved excellent silicon correlation using the company's Analog FastSPICE Platform for accurate performance characterization of a 40nm nanometer Phase-Locked Loop (PLL) clocking circuit IP, targeted to networking and cloud computing applications requiring over 100 Gbps data transfer rates.
"We have designed the lowest jitter LC-Tank PLL in the industry, supporting SoC applications requiring over 100 Gbps data transfer rates," said Mahesh Tirupattur, Executive Vice president at Analog Bits. "Our design is silicon-proven in TSMC's 40nm G process, and is now moving to 28nm. We used the AFS Platform to perform closed-loop transistor-level PLL characterization including parasitic and device noise effects. We achieved excellent silicon correlation, smashing the original 300-femtosecond goal across broad integration range --- a first for clocking IP."
The Analog FastSPICE Platform is the world's fastest nanometer circuit verification platform for analog, RF, mixed-signal, and custom digital circuits. The AFS Platform delivers foundry-certified nanometer SPICE accuracy 5x-10x faster than any other simulator on a single core and an additional 2x-4x performance with multithreading.
For circuit characterization, the AFS Platform includes the industry's only comprehensive silicon-accurate device noise analysis and delivers near-linear performance scaling with the number of cores. For large circuits, it delivers >10M-element capacity, the industry's fastest near-SPICE-accurate simulation, and co-simulation with leading VerilogŪ simulators. Available licenses include AFS circuit simulation, AFS Transient Noise Analysis, AFS RF Analysis, AFS Co-Simulation, and AFS Nano SPICE.
"We are very excited to see the silicon success of Analog Bits' breakthrough 40nm PLL IP design," said Ravi Subramanian, President and CEO of Berkeley Design Automation. "It is a formidable challenge to deliver jitter performance requirements at hundreds of femtoseconds in 40nm CMOS technology because of numerous complex effects due to parasitics, device noise, and nonlinear closed-loop behavior - and AFS once again delivered silicon-accurate results. We are proud to celebrate Analog Bits silicon success."
About Berkeley Design Automation
Berkeley Design Automation, Inc. is the recognized leader in nanometer circuit verification. The company combines the world's fastest nanometer circuit verification platform, Analog FastSPICE, with exceptional application expertise to uniquely address nanometer circuit design challenges. More than 100 companies rely on Berkeley Design Automation to verify their nanometer-scale circuits. Berkeley Design Automation has received numerous industry awards and is widely recognized for its technology leadership and contributions to the electronics industry. The company is privately held and backed by Woodside Fund, Bessemer Venture Partners, Panasonic Corp., NTT Corp., IT-Farm, and MUFJ Capital. For more information, visit
About Analog Bits
Founded in 1995, Analog Bits, Inc. is the leading supplier of low power, customizable analog IP for easy and reliable integration into modern CMOS digital chips. Our products include precision clocking macros such as PLL's & DLL's, programmable interconnect solutions such as multi-protocol SERDES/PMA and programmable I/O's as well as specialized memories such as high-speed SRAMs and TCAMs. With billions of uses of IP fabricated in customer silicon from 0.35-um to 28-nm processes, Analog Bits is the premier analog IP supplier with an outstanding heritage of "first time working silicon" at merchant foundries and IDMs. For more information, visit
Source: Berkeley Design Automation (press release)
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