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Posted: Mar 29, 2012
A simple and effective approach to improve device performance of pentacene thin film transistors
(Nanowerk News) Organic thin film transistors (TFTs) have attracted much attention due to their wide and potential applications in, e.g., flexible displays, radio frequency identification cards, and sensors. Pentacene TFTs, in which gold (Au) source/drain electrodes are commonly used as the charge-injecting metal, are particularly attractive on account of their large mobility (~ 1 cm2 V-1 s-1) and high on/off ratios (>105), particularly when compared to those for amorphous silicon TFTs. Although some promising progress has been achieved, the threshold voltage (VT) of the pentacene TFTs is still too high (~ -20 V) for practical applications.
One method to reduce VT is to replace the most commonly used silicon dioxide (SiO2) substrate with a dielectric substrate having a high dielectric constant (high-κ). However, using high-κ dielectrics could decrease the charge-carrier mobility owing to the high dipolar disorder at the interface, in addition to a high leakage current and low dielectric strength. To date, reducing VT of the pentacene TFTs on SiO2 substrates is still a big challenge, especially in maintaining the high mobility.
In this case, VT decreased remarkably from ca. -20 V to a few volts (below -7.6 V), while the mobility increased 1.5 times after the insertion of the interlayer. The performance enhancement could be attributed to the reduction of the carrier-injection barrier between the Au source/drain electrodes and the pentacene active layer due to the involvement of the MPc interlayer.
The report suggests a simple and effective way to fabricate low-threshold-voltage pentacene TFTs with high mobility on SiO2 dielectric substrates, which should be helpful for promoting their use in practical applications.