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Posted: September 25, 2007
Leading IC Engineers to Gather in Albany at SEMATECH Workshop on 3D Chips
(Nanowerk News) An International SEMATECH-sponsored workshop will bring leading engineers here Oct. 11-12 to share insights on design and thermal challenges for next-generation, three-dimensional integrated circuits (3D ICs).
The meeting, “Thermal and Design Issues in 3D ICs,” will explore the nature and magnitude of thermal challenges to 3D IC technology, which aims for greater functionality by stacking silicon chips connected with through-silicon vias (TSVs). The meeting at the Holiday Inn on Wolf Road also will address the broader architecture, design, and CAD tool challenges that must be met to exploit the full potential of 3D ICs.
“This approach has many potential advantages – improved electrical performance, lower power consumption, integration of different device types, and lower cost. However, it also presents many new challenges to the design community, including how to deal with higher power densities,” said Larry Smith, SEMATECH engineer and workshop chair. “Our goal is to present a better understanding of these issues, and of the design methodologies and thermal management solutions that address them.”
The workshop’s program of leading 3D technologists and topics includes:
-- Overview of 3D Technologies, Thermal and Design Issues
-- Phil Garrou, Microelectronic Consultants of North Carolina,
"Introduction to 3D Technologies"
-- Mike Ignatowski, IBM, "Challenges and Opportunities for
Exploiting 3D Technology in System Designs"
-- Dr. Takafumi Fukushima, Tohoku University, "Thermal Issues of
-- Applications, Opportunities, Program Scopes
-- John Magerlein, IBM, "Thermal Limits and Approaches for 3D
-- Bob Jones, Freescale, "Technology, Design and Applications of
-- Muhannad Bakir, Georgia Tech, "Limits and Opportunities for
Heat Removal and Power Delivery to Gigascale Systems"
-- Michael Fritze, DARPA and Michael Steer, NCSU, "Thermal
Challenges in DARPA's 3DIC Technology Portfolio"
-- Modeling, Design, and Architecture
-- Ruchir Puri, IBM, "3D Design and CAD Challenges"
-- Yuan Xie, Penn State, "Design Space Exploration for 3D
-- Jason Cong, UCLA, "Thermal-Aware Physical Design for 3D ICs"
-- Tan Chuan Seng, NTU-Singapore, "Heat Removal Enhancement of
3D Interconnects Using Copper Wafer Bonding"
-- Rajiv Joshi, IBM, "Thermal Analysis of Bonded Wafers"
-- Seri Lee, Nextreme, "Thermoelectric Cooling for 3D Chip Stacks"
The workshop is designed for IC manufacturers, materials suppliers, CAD suppliers and users, and 3D-TSV researchers, and is being held in conjunction with the Advanced Metallization Conference on Oct. 9-11 at the Albany Marriott Hotel. It is being co-sponsored by the ACM/SIGDA Physical Design Technical Committee. Interested persons are encouraged to visit the workshop website at http://www.sematech.org/meetings/announcements/8334/.
For 20 years, SEMATECH® (www.sematech.org) has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Today, we continue accelerating the next technology revolution with our nanoelectronics and emerging technology partners.