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Posted: December 5, 2007
SEMATECH to Reveal New Pathways for Advanced Transistor Scaling at IEDM
(Nanowerk News) SEMATECH's continuing leadership in developing alternative transistor materials and processes for advanced semiconductors will be further demonstrated here next week at the 2007 IEEE International Electron Devices Meeting (IEDM).
Engineers from SEMATECH's Front End Processes (FEP) Division will present five technical papers on high-k metal gate stack and high-mobility channel materials during the prestigious annual conference, Dec. 10-12 in the Hilton Washington. SEMATECH also will host an invitational pre-conference workshop on technical and manufacturing challenges affecting the use of III-V materials in CMOS devices.
"Our presence at IEDM is a fitting climax to a year of solid progress in providing our members and the industry with new materials for transistor scaling," said Raj Jammy, FEP director. "We've developed a high-k metal gate stack solutions that are process-driven, flexible, and open to external evaluation. We've also charted a course for the heterogeneous integration of advanced gate stack and high-mobility channel materials onto silicon. Our continuing leadership in materials is helping pave the way for 22nm feature technology and beyond."
Supporting that goal will be SEMATECH's workshop, "III-V CMOS on Si: Technical and Manufacturing Needs." Co-sponsored by Aixtron AG, the workshop will include an opening talk by Robert Chau, Intel Senior Fellow and director of transistor research and nanotechnology in Intel's Technology and Manufacturing Group. Other speakers will focus on topics leading to an early understanding of key issues in the large-scale manufacturing use of elements in columns III, IV and V of the periodic table.
At the subsequent IEDM conference, SEMATECH technologists will release new details on their cutting-edge metal gate technology. Another SEMATECH paper will provide new insights on application of flash-annealing to form ultra-shallow junctions with high-k metal gate devices and address associated defect issues.
Following is a summary of the SEMATECH papers' session times, findings, titles, and lead authors:
-- Session 3, at 2:25 p.m. Monday, Dec. 10: "Flexible, Simplified CMOS on Si(110) with Metal Gate/High-k for HP and LSTP" (Rusty Harris). High-k/metal gates on NMOS Si(110) demonstrate respectable output performance due to velocity saturation of electrons. As a result, Si(110) may provide significant performance improvement for HP and LSTP without the process complexity typical of mixed-orientation CMOS approaches.
-- Session 13 at 9:55 a.m. Tuesday, Dec. 11: "Mechanism of Vfb Roll-off with High Workfunction Metal Gate and Low Temperature Oxygen Incorporation to Achieve PMOS Band Edge Workfunction" (S.C. Song). The phenomenon of flat-band voltage (Vfb) rolloff is successfully explained by progressive oxygen vacancy generation in high-k materials.
-- Session 13 at 11:35 a.m. Tuesday: "Impact of Flash Annealing on Performance and Reliability of High-k/Metal-Gate MOSFETs for sub-45nm CMOS" (Pankaj Kalra). Flash annealing can be used to form ultra-shallow junctions to meet requirements for sub-45nmn CMOS technology, and with optimized post-metallization treatment is fully compatible with advanced gate stacks. This marks the first successful use of flash annealing on real devices, solving a number of process issues with proprietary data provided exclusively to SEMATECH members.
-- Session 20 at 4:50 p.m. Tuesday: "Aggressively Scaled High-k Gate Dielectric with Excellent Performance and High Temperature Stability for 32nm and Beyond" (Prasanna Sivasubramani). SEMATECH engineers have successfully demonstrated the effectiveness of a higher-k gate material, hafnium-titanium-silicon-oxynitride (HfTiSiON), for the sub-32 nm technology generation. Reported for the first time, SEMATECH engineers were able to address the thermodynamic instability of TiO2-containing dielectrics.
-- Session 28 at 11:35 a.m. Wednesday, Dec. 12: "Demonstration of High-Performance PMOSFETs Using Si/SxGe1-x/Si Quantum Wells with High-k Metal Gate Stacks and Uniaxial Strain Additivity for 22nm Technology and Beyond" (Sagar Suthram). In another first, SEMATECH engineers have demonstrated that strain-enhanced silicon-germanium (SiGe) and germanium-based channels show drive current improvements similar to silicon under strain. Experimental findings also indicate that PMOSFETs with strained quantum wells show good performance qualities comparable to silicon.
More information on FEP's accomplishments this year can be found at these links:
-- "SEMATECH Engineers Reveal Further Details of Trailblazing Work on Practical High-K Metal Gate Systems for 45nm And Beyond." www.sematech.org/corporate/news/releases/20070820.htm.
-- "SEMATECH Develops Dual Metal Gates for high-k CMOS Devices; Completes Quest with pMOS Breakthrough." www.sematech.org/corporate/news/releases/20070126.htm.
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