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Posted: Sep 25, 2013
Perfecting nanoscale circuits
(Nanowerk News) The downside of scaling nanoelectronic feature sizes is increasing unreliability of performance and power (hence robustness). An EU-supported project has developed techniques to tackle this problem.
As in other sectors and industries, cost control, production efficiency, cycle time and yield factors are also critical benchmarks for nanoelectronics. The major challenge of nanoscaling complementary metal-oxide semiconductors (CMOSs) is controlling variation in geometric tolerances such as edges and roughness. This results in the performance and power of circuits becoming extremely sensitive to uncontrollable statistical process variation (PV).
The EU-funded MANON project brought together academia and industry, including small businesses to create PV-aware and PV-robust circuit design techniques, tools and models.
The project focused on using multi-objective optimisation algorithms, symbolic techniques and numerical statistical simulation. It also promoted the exchange of know-how and good practice on industrial design, real-life test cases and electronic design automation (EDA) software. MANON investigated three different approaches, including the use of symbolic model order reduction (SMOR) techniques combined with neural networks (NNs).
The MANON project target is to develop an, as much as possible, automatic method to generate parameterized behavioural models, including the most relevant statistical process information, in order to: make statistical analysis and simulation available on system level, reduce the effort for model generation, ensure model simulation accuracy and also extend the methodology also to strong non-linear IC’s.
Models developed by the project will enable designers to perform system-level verification and customers to fine-tune designs based on responses to operating conditions and PV.
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