(Nanowerk Spotlight) Electronic memory devices are increasingly expected to provide not only greater storage density, but also faster access to information. As storage density increases, however, power consumption and unwanted heat generation also increase, and the fidelity of accessing the memory is frequently diminished. Various platforms exist to overcome these hurdles and, increasingly, graphene finds it way into computer memory technology. The most recent example are experiments that demonstrate the benefits of graphene as a platform for flash memory which show the potential to exceed the performance of current flash memory technology by utilizing the intrinsic properties of graphene.
"By implementing graphene into a well-known memory structure – flash memory – we find that current flash memory technology can be further scaled and advanced to meet the high-demands of large-storage-density in electronic products," Emil B. Song, a PhD student in the Device Research Laboratory at UCLA's Electrical Engineering Department, tells Nanowerk.
Song is co-first author of a paper in the August 22, 2011 online edition of ACS Nano ("Graphene Flash Memory"), where a team from UCLA, IBM's T.J. Watson Research Center, Samsung Electronics, Aerospace Corporation, and the University of Queensland, team led by Kang Wang (Director of Functional Engineered Nano Architectonics and Western Institute of Nanoelectronics) demonstrates results that suggest that graphene may be instrumental in the next round of miniaturization of flash memory.
Song explains that graphene has the potential to exceed the performance of current flash memory technology by utilizing three exceptional intrinsic properties of graphene – high density of states, high work function, and atomic thinness – when compared to the conventional materials used for the two types of flash memory structures – floating-gate flash memory, which is the current industry standard, and charge-trap flash memory, which is an emerging technology.
"These unique properties provide improvements for flash memory in memory window, retention time, and cell-to-cell interference, respectively" he says. "The enhanced memory window and retention time increases the fidelity of information stored in the memory device. The reduction of cell-to-cell interference offers a solution to achieve higher-density-storage memory devices."
Graphene flash memory has a larger memory window, longer retention time, and suffer very little from cell-to-cell interference. (Graphic: Emil B. Song, UCLA)
Song and his collaborators also point out that, by utilizing graphene's unique properties, flash memory can be further scaled beyond the 20nm node, which is what polysilicon can achieve, and result in even greater storage-density.
Three important figures of merit for flash memory are the memory window (which refers to the shift in threshold voltage of the memory device when switching from the 0 to 1 binary states), retention time (which refers to the potential lifetime of nonvolatile storage), and cell-to-cell interference (which is the most critical scaling barrier for flash memory devices).
In order to investigate the electrical characteristics of graphene flash memory (GFM), the research team fabricated several memory devices according to the fabrication process shown below:
GFM fabrication processes. (a) Piranha rinsing and BOE dip of Si substrate. (b) Tunnel oxide (SiO2) formation through RTO. (c) CVD graphene growth and transfer. (d) Control oxide (Al2O3) deposition by ALD. (e) Gate-electrode (Ti/Al/Au) formation using standard photolithography technique. (f) Device isolation by Cl2 dry etching (Al2O3) and O2 plasma. Finally, substrate contact (Pt) by e-beam evaporation. (Reprinted with permission from American Chemical Society)
In their experiments, the team found that their GFM displays a wide memory window of ∼6 V at significantly low program/erase voltages of ±7 V. GFM also shows a long retention time of more than 10 years at room temperature. Additionally, simulations suggest that GFM suffers very little from cell-to-cell interference, potentially enabling scaling down far beyond current state-of-the-art flash memory devices.
"Our next step will be to find ways to actually implement the individual storage elements in an integrated circuit and study the details of operational speed and energy dissipation," he describes the team's plan. "The challenges will be finding a stable processing scheme for IC and chip architecture to achieve even larger-storage-density, faster operation speed, and lower power consumption."
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