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Posted: Apr 29, 2014
Carbon nanotube computer for the masses gets closer
(Nanowerk Spotlight) Carbon nanotube (CNT) transistors are attractive as a basis for dense, energy efficient integrated circuits for future computers. CNT-based circuits promise both increased performance and energy efficiency over circuits today. This projected improvement is substantial – over an order of magnitude improvement in energy-delay product. For instance, electronic circuits can run three times faster while consuming only one third of the energy. There are many applications, from traditional computers to smartphones to big data, where improving both the performance and energy efficiency have significant implications.
So far, though, most of the accomplishments in building CNT circuits have come at the single-nanotube level. Researchers have been struggling with two major obstacles in building CNT-based circuits: the presence of metallic CNTs – as opposed to more desirable semiconducting ones – in the circuits leads to short circuits, excessive power leakage and susceptibility to noise; and a 'perfect' alignment of nanotubes has proved all but impossible to achieve, introducing detrimental stray conducting paths and faulty functionality into the circuits.
However, these techniques – a set of very large scale integration (VLSI)-compatible design and processing techniques that overcome both the presence of mis-positioned and metallic CNTs within a circuit in a scalable manner – have only been applied to large CNT field-effect transistors (CNFETs). Questions remained as to whether these techniques could be applied to highly scaled CNFETs as well.
In new work coming out of Mitra's and Wong's labs at Stanford, the researchers now have demonstrated that these techniques can be applied successfully to highly-scaled CNFETs, resulting in the ability to fabricate, in a scalable manner, larger-scale CNFET circuits at highly scaled technology nodes. The channel lengths are ranging from 90 nm to sub-20 nm.
Scanning electron microscopy of an integrated CNFET IR sensor and interface circuit, along with processing steps. The first lithography step defines 1 µm channel lengths, followed by two source-drain extensions (defined through aligned electron-beam lithography) to form 32 nm channel lengths. (Reprinted with permission from American Chemical Society) (click image to enlarge)
"Larger CNT-based circuits, like our recent CNT computer, have all been demonstrated with rather large CNFETs at 1 µm channel lengths," Max Shulaker, a doctoral student in Mitra's group and the paper's first author, tells Nanowerk. "However, circuits today use highly-scaled transistors, with channel lengths well below 100 nm. In order to achieve all of the benefits of CNFET-based circuits, the CNFETs must all be scaled-down to these highly-scaled dimensions."
In their paper, the team demonstrates the first scalable approach to realizing CNFET digital circuits at these highly scaled technology nodes, with devices up to sub-20 nm channel lengths. With the ability to scale to smaller technology nodes, the Stanford team's VLSI-compatible circuits obtain major improvements in operating frequency (∼100x) and power consumption (∼2500x) compared to previous CNFET-based sensor interface work.
As a demonstration, they show a 32 nm channel length fully integrated CNFET infrared light sensor and interface system, operating at ~100 kHz while consuming only 130 nW at 2 V supply voltage.
This research has been another step towards fully realizing the energy efficiency and performance of scaled CNFET circuits; however, additional obstacles, such as increasing CNT density and improving contact resistance, must be overcome.
"There have been promising demonstrations of approaches capable of overcoming these obstacles, which together with this work hopefully bring us one step closer to realizing the exciting potential of highly scaled CNFET circuits as a digital VLSI technology," shulaker concludes.