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Posted: Sep 18, 2008
New architecture for single-electron devices allows CMOS-compatible large-scale fabrication
(Nanowerk Spotlight) For nanoelectronics applications like single-electron devices to become practical, everyday items, they need to move from the highly individual and customized fabrication process typically found in laboratories to an automated, high-throughput and industrial-scale production environment. The reason this hasn't happened yet is that the various nanoscale pattern definition techniques used today – such as e-beam lithography, mechanically controllable break junctions, electromigration, electrodeposition, nanoscale oxidation, and scanning tunneling microscopy – generally are not suitable for large-scale parallel processing.
The fabrication of single-electron devices requires nanoscale geometrical arrangement of device components, that is, source and drain electrodes and Coulomb islands. Developing methods to fabricate nanoscale devices in large numbers at a time has been one of the major efforts of the nanotechnology community. A new study now demonstrates that this can be done with complete parallel processing using CMOS-compatible processes and materials. Furthermore, these single-electron devices can operate at room temperature, an essential requirement for practical implementations.
"We have demonstrated chip-level fabrication of room-temperature single-electron devices that does not use any of the sophisticated nanoscale pattern definition techniques that generally have intrinsic limitations for large-scale processing" Dr. Seong Jin Koh< explains to Nanowerk. "Except for electrical measurements at the end, at no time was any device treated individually."
Koh, an Assistant Professor in the Department of Materials Science and Engineering at the University of Texas at Arlington, together with his team has used a novel geometry and processes in which source and drain electrodes are vertically separated by thin dielectric films and are self-aligned, and the nanoparticles are attached on the sidewall of dielectric film acting as Coulomb islands.
This approach, described in a recent paper in Nature Nanotechnology, allows nanoscale geometrical control in complete parallel processing, paving a way toward fabrication of integrated systems of single-electron devices ("CMOS-compatible fabrication of room-temperature single-electron devices"). Fabrication of other nanoscale devices and sensors may also benefit from the approach described in this study.
"Our goal was to realize a nanoscale geometrical arrangement of device components in a way that can be achieved over a large area with parallel processing" says Koh. He then explains the three key aspects to this approach:
"First, the separation of the two electrodes is defined by the thickness of the intervening dielectric film and, therefore, can be controlled with sub-nanometer-scale precision over a large area by using film deposition techniques such as plasma-enhanced chemical vapor deposition (PECVD) and atomic-layer deposition (ALD).
"Second, the drain, dielectric layer and source are vertically self-aligned, maintaining the integrity of the source–drain gap along the periphery of the source/drain electrodes.
"Third, the Coulomb islands are positioned on the exposed sidewall of the dielectric film and, therefore, the lateral length may assume an arbitrary dimension. This liberty of arbitrarily choosing the lateral dimension of the device structure allows the use of photolithography and associated pattern definition processes within the framework of CMOS fabrication technology, enabling single-electron device fabrication in complete parallel processing."
Fabrication of single-electron devices. a–c, Schematic of the key process steps for the fabrication of the single-electron device structure. Definition of drain electrode through photolithography, deposition of chromium and lift-off (a). Vertical etching of PECVD oxide and top portion of source electrode using RIE. The drain electrode (Cr) is used as a hard mask and the sidewall of the PECVD oxide is formed along the periphery of the drain electrode (b). Attachment of nanoparticles on the PECVD oxide sidewall by immersing the wafer into gold nanoparticle colloid. Before immersion, the SAMs of (3-aminopropyl)triethoxysilane (APTES, (C2H5O)3-Si-(CH2)3-NH2) are formed to attract negatively charged gold nanoparticles (c). d–g, Schematic of process flow involving four photomask
steps (only one device unit is shown; schematic is not to scale). First mask step: the source electrodes (Cr) are defined on the isolation oxide through
photolithography/chromium deposition/lift-off (d). Second mask step: using processes a–c, each single-electron device is fabricated on top of every source
electrode (e). Third mask step: the wafer is passivated with silicon oxide, followed by formation of vias through photolithography and RIE (f). Fourth mask step:
the bond pads are defined using photolithography, deposition of gold and lift-off. Vias are filled with gold, connecting the source and drain electrodes to
bond pads (g). h, Photograph of an actual fabricated chip mounted on a chip carrier. (Reprinted with permission from Nature Publishing Group)
The process developed by Koh and his team could find broad applications – basically all electronic devices that require extremely low power consumption and a high packing density could benefit from it.
In order to simplify device fabrication, Koh and his team used only one type of SAMs layer (APTES) to functionalize both the oxide sidewalls and source/drain electrodes.
"Although this procedure is sufficient to demonstrate parallel fabrication of arrays of room-temperature single-electron transistors, it also leads to stray nanoparticle attachment" says Koh. "With such non-ideal Coulomb island positioning, we have produced room-temperature single-electron transistors with a success rate close to 1%."
Of course, in practical device fabrication a much higher yield would be required and that will necessitate that the nanoparticles must be placed precisely and exclusively on the exposed sidewalls rather than randomly.
Koh mentions that one method by which this can be done is the selective formation of different SAMs on different surfaces to direct the nanoparticles to the desired locations, for example, positively charged SAMs on oxide sidewalls and negatively charged SAMs on source/drain electrodes.
"We have demonstrated the effectiveness of this selective surface functionalization on precise nanoparticle placement for our device geometry" he says. "Incorporating this method of controlled nanoparticle placement into our single-electron device fabrication is currently under way."