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Posted: Oct 26, 2006
Giant enhancement of the carrier mobility in silicon nanowires
(Nanowerk Spotlight) 'Carrier mobility' is a major factor in determining the speed of electronic devices. Aggressive scaling of the complementary metal-oxide-semiconductor (CMOS) transistor technology requires a high drive current, which depends on the charge carrier mobility. As the dimensions of nanoelectronic circuits continue to shrink, it is important that the carrier mobility does not deteriorate and, if possible, improves. The search for nanostructures where the carrier mobility values can be preserved or even improved continues owing to the extremely high technological pay-off if successful. Nanowires represent a convenient system to understand the effects of low dimensionality on the carrier drift mobility. One can also look at nanowires as an ultimately scaled transistor channel. New research at the University of California - Riverside demonstrates a method for the significant enhancement of the carrier mobility in silicon nanowires. Such mobility enhancement would allow to make smaller and faster transistors and improve heat removal.
"Phonons, i.e. quanta of the crystal lattice vibrations, manifest themselves practically in all electrical, thermal and optical phenomena in semiconductors" says Balandin. "Phonons carry heat and scatter electrons. Reduction of the feature size of electronic devices to the nanometer scale creates extra resistance for the electrical current flow and complicates heat removal from the downscaled electronic devices. On the other hand, it opens up an exciting opportunity for engineering phonon spectrum in nanostructures and, possibly, achieving enhanced operation of nanodevices."
The theoretical results obtained by Fonoberov and Balandin suggest that the electron mobility in silicon nanowires embedded within diamond can be made two orders of magnitude higher at the temperature of 10 K and by a factor of two higher at room temperature than the mobility in a free-standing silicon nanowire.
The importance of this result for the downscaled architectures and possible silicon-carbon nanoelectronic devices is augmented by an extra benefit of diamond, a superior heat conductor, for thermal management. The use of microcrystalline diamond (µ-D) or diamond-like carbon (DLC) can help to offset the high cost and achieve CMOS compatibility. The measurements of the thermal conductivity of µ-D thin films on silicon conducted in Balandin’s Nano-Device Laboratory (NDL) indicate rather large values even for small crystalline sizes (the results are soon to appear in Applied Physics Letters).
Balandin explains to Nanowerk the significance of his group's findings: "Our results revise the long-standing belief that the spatial-confinement induced modification of the phonon spectrum is always detrimental to the carrier mobility."
Balandin points out that previous methods of the carrier mobility enhancement, some of which are used by industry in the design of computer chips, utilize the strain engineering in the lattice mismatched layers.
"For example" he says, "the strain-induced band-structure modification in Si/SiGe films is found to have a strong impact on the carrier mobility and transistor performance. At the same time, the strain engineering approach based on utilization of SiGe layers has a serious problem related to the thermal budget. SiGe and other alloys have an order of magnitude smaller thermal conductivity preventing the heat escape from the transistor channel. Implementation of the alternative and beyond-CMOS transistor concepts requires novel drastic methods for the mobility enhancement, which would not deteriorate the thermal management."
The results obtained by NDL group offer an alternative method, which does not use strain, and can actually improve the thermal management. These findings could play an important role for the fabrication of future nanoelectronic devices and circuits. Balandin's NDL lab is now developing a phonon engineering concept for the improvement of the electron transport in nanoscale devices and the thermal management of nanoelectronics.
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