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Posted: June 5, 2010
Tabula to Demonstrate the ABAX 40nm, 48-Channel, Multi-protocol 6.5Gbps SERDES at DAC 2010
(Nanowerk News) Tabula, Inc., a privately held fabless semiconductor company and developer of the ABAX family of 3-D Programmable Logic Devices (3PLDs), will be demonstrating its 40nm ABAX product family at the Design Automation Conference held June 13-18th in Anaheim, California at the TSMC Booth #294. Tabula will exhibit with its IP partner, Analog Bits, Inc., the global market leader in providing customized transistor level IP components for CMOS logic processes and who developed the PMA portion of the physical layer SERDES, PLLs, DLLs, and I/Os embedded in ABAX.
At the TSMC booth #294 Tabula will demonstrate:
- ABAX 48 SERDES channels on chip
- Each SERDES can run at 6.5Gbps and supports multiple protocols
Companies designing and manufacturing communications infrastructure, industrial, medical, test, and military/aerospace applications will not want to miss the opportunity to see Tabula's recently announced ABAX 3PLDs product family. Based on the company's groundbreaking Spacetime 3-Dimensional programmable logic architecture, ABAX delivers a logic platform that blends the programmability and fast time-to-market of FPGAs with the performance and volume price points traditionally associated with ASICs and ASSPs.
To schedule a meeting with the Tabula sales and marketing team, please register today: https://www.tabula.com/support/dac_register.php
"Leveraging our innovative Spacetime 3D architecture, the ABAX 3PLD products deliver unprecedented price/ performance for programmable logic," said Alain Bismuth, VP of Marketing at Tabula. "Deployed on TSMC 40nm process, the family offers a very rich set of features and we look forward to demonstrating our robust 48-channel, multi-protocol 6.5Gbps SERDES at DAC 2010."
The silicon IP developed by Analog Bits and implemented in the ABAX 3PLD demo includes 68 programmable PLLs operating in excess of 1.8 GHz, 48 lanes of 6.5Gbps SERDES physical layer capable of supporting multiple standards (Gigabit Ethernet, PCI-Express, SATA, XAUI and other CDR protocols) and programmable I/Os and DLLs capable of supporting DDR-2 and DDR-3-compatible memory interfaces. Each of these physical layers have been thoroughly tested and qualified as compatible with TSMC's 40nm manufacturing process.
"At Analog Bits our core business value and focus is to be a trusted partner for our clients designing in leading edge process technologies such as TSMC 40nm," says Mahesh Tirupattur, Executive VP, Analog Bits. "We are pleased to enable Tabula's breakthrough ABAX 3PLD devices to communicate with the external world with our highly reliable and differentiated connectivity and clocking IP solution."
About Analog Bits
Founded in 1995 and headquartered in Silicon Valley, Analog Bits, Inc. specializes in designing transistor level IP components fully customized for easy and reliable integration into digital chips. Products include precision clocking IP macros such as PLLs, DLLs, and programmable interconnect solutions such as multi-protocol SERDES/PMA, programmable I/Os and specialized memories such as high-speed SRAMs, T-CAMs. With over billions of IPs in silicon from 0.35-um to 32/28-nm processes, Analog Bits is the world's premier custom IP supplier with a flawless track record of "first time working silicon" at merchant foundries and prestigious IDMs.
Tabula is a privately held fabless semiconductor company developing 3-D Programmable Logic Devices. Its ABAX family of 3PLDs, based on Tabula's patented Spacetime architecture, sets new density, performance, and affordability benchmarks for programmable logic, memory, and signal processing. Headquartered in Santa Clara, California, Tabula has assembled a leadership team consisting of industry veterans and successful entrepreneurs. The company is backed by top-tier investors with a long-term view toward enduring market leadership.