Synopsys Delivers 28-nm Design Solutions and Advanced System-Level Capabilities for TSMC Reference Flow 12.0

(Nanowerk News) Synopsys, Inc., a world leader in software and IP for semiconductor design, verification and manufacturing, has announced that it is delivering comprehensive design enablement for TSMC's 28-nm process technology, integrated manufacturing compliance and an advanced system-level prototyping solution, with TSMC Reference Flow 12.0. New features of the flow include virtual prototyping and high-level synthesis linked to TSMC's advanced processes, expanded manufacturing compliance capabilities and full support of TSMC's latest 28-nm design rules and models within Synopsys' Galaxy™ Implementation Platform. With the new tool capabilities and system-level design integration, designers gain productivity, shortened time-to-market and faster time-to-volume using TSMC's 28-nm process technology.
"TSMC and Synopsys collaborated on Reference Flow 12.0 to increase productivity and design quality with an optimized design methodology for our mutual customers," said Suk Lee, director of design infrastructure marketing at TSMC. "The combination of Synopsys tools, IP and system-level design and prototyping capabilities with TSMC's complete 28-nm design infrastructure and advanced process technology provides designers with a comprehensive solution that addresses manufacturability while enabling design for optimized performance."
Synopsys has extended Reference Flow 12.0 to deliver a consistent and comprehensive methodology for earlier development and faster verification of software stacks and hardware platforms using Synopsys' Virtual Prototyping and Synphony C Compiler high-level synthesis solutions. The virtual prototype authoring tool, combined with Synopsys' open transaction-level-modeling (TLM)-2.0 model library, enables designers to quickly and automatically generate and integrate models and interconnects to create virtual prototypes. The integration of TSMC's Power Performance Area model in the flow allows hardware and software designers to make TSMC technology node- and software-specific tradeoffs months earlier in the design flow. The system-level flow links SystemC™ TLM 2.0 and RTL models in Synopsys' VCS®- based verification solution using the UVM methodology and hybrid virtual prototypes, enabling verification environment reuse and software-driven verification. Synphony C Compiler high-level synthesis has been optimized for TSMC's advanced process technologies, allowing designers to quickly achieve performance- and power-optimized results using high-level C/C++ code.
The flow includes a comprehensive ARM® Cortex™-A9 MPCore™ Fast Model-based reference Virtual Prototype, which has been extended with a TSMC example H.264 video subsystem. In conjunction with the included Linux SMP kernel and file system, this example serves as a practical template for early hardware/software stack integration and demonstrates the full virtual prototyping debug and analysis capabilities. Fully documented reference design examples for Synphony C Compiler are also included in the flow.
The Synopsys Galaxy Implementation Platform features comprehensive support for TSMC's latest 28-nm design rules for manufacturing compliance from physical design through to signoff. Additionally, Reference Flow 12.0 includes IC Compiler's leakage optimization engine for final-stage leakage recovery on a close-to-tapeout design. Reference Flow 12.0 adds IC Validator's patented pattern-matching technology to extend the advantage of IC Compiler's In-Design physical verification by enabling fast detection and automated repair of manufacturing-limiting layout patterns.
"Designers are looking to make the most of TSMC's most advanced process nodes through a convergent and predictable path that helps them successfully develop a system-on-chip from system-level concept to silicon," said Rich Goldman, vice president of corporate marketing and strategic alliances at Synopsys. "Synopsys and TSMC team to deliver unique analysis, verification and implementation solutions in Reference Flow 12.0, offering our mutual customers an optimized path to achieve their aggressive system-on-chip design goals."
Source: Synopsys (press release)
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