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Posted: February 1, 2008
EoPlex CEO Will Speak on Filling the Gap Between Nano and 'Just Plain Miniature' Devices
(Nanowerk News) Arthur L. Chait will present to the IEEE Components, Packaging and Manufacturing Technology Society of Silicon Valley on Wednesday, February 13th, 6:30 p.m. at the Sunnyvale Ramada Inn.
Mr. Chait will note that a great deal of progress has been made in the field of nano and related "tiny" technologies. Unfortunately, the technology to link the tiny world to the macro world has not kept pace. The space between nano and macro is immense. At the nano end are self-assembling structures and semiconductor processes that deal in angstroms; and at the macro end are conventional machining and assembly techniques. Between these two extremes there is a gap where engineers struggle to make low-cost devices with complex 3-D structures containing multiple materials that are "Just Plain Miniature" (JPM). This talk will discuss the meso-scale, HVPF™ technology and describe applications including: cell phone antennas, energy harvesters to replace batteries, thermal management devices and microreactors for use in fuel cells.
Dinner tickets are $30.00 each. The presentation-only session at 7:30 p.m. is offered at no cost. The Sunnyvale Ramada Inn is located at 1217 Wildwood Avenue, Freeway 101 frontage road, between Lawrence Expressway and Great America Parkway, Sunnyvale, (800.888.3899). Tickets may be purchased through PayPal. Reserve in advance by email to Janis Karklins, [email protected]
The IEEE Components, Packaging and Manufacturing Technology (CPMT) Society is the leading international forum for scientists and engineers engaged in the research, design and development of revolutionary advances in microsystems packaging and manufacture. The non-profit Society helps professionals through its journals, conferences and workshops, committee activities, local chapter events, educational programs and awards. For more information, visit http://www.cpmt.org/. CPMT is part of the IEEE (Institute of Electrical and Electronics Engineers), the world's largest professional technology association. This non-profit organization develops, defines and reviews electronics and computer science standards. Standards developed by the IEEE often become international standards. Membership includes deans and provosts of every major engineering university and college throughout the world. Membership also includes engineering managers and corporate and financial executives.
About Arthur L. Chait
Arthur L. Chait joined EoPlex in 2002 and was elected Chairman of the Board in 2003. EoPlex is a Silicon Valley start-up that utilizes new technology to manufacture low-cost ceramic-metal components for miniature energy devices, sensors, fuel cells, pumps, packages and circuits. Mr. Chait has raised two rounds of VC funding and the company is now backed by Draper Fisher Jurvetson, ATA Ventures, Labrador Ventures, and Draper Richards. Prior to EoPlex, Mr. Chait was with Solectron (NYSE) as Senior VP Global Accounts where he had revenue responsibility of over $10 billion/year with customers including: IBM, Cisco, Dell, Apple, Ericsson, SUN, Nortel, Nokia, HP/Compaq, Motorola, and Lucent. Mr. Chait's prior experience also includes: GM Zitel (NASDAQ) where he created the software division; Senior VP at Stanford Research Institute with responsibility for 600 staff and all international offices; Booz Allen & Hamilton where he managed assignments in technology strategy for major OEMs; and Dresser/Halliburton where he was a research director in advanced materials. Mr. Chait holds an MBA from the University of Pittsburgh and a BS in Materials Engineering from Rutgers University and was also awarded the Steinmetz Medal from GE.
About EoPlex Technologies, Inc.
EoPlex Technologies, Inc. produces components using innovative deposition techniques based on custom printing equipment and proprietary "inks" that carry ceramic, metallic or polymer materials to millions of locations. This allows the manufacture of components with integrated chambers, channels, sensors, circuits, reactors, energy scavengers and other features. Many parts are created simultaneously in large panels and the only tooling required is low-cost printing masks. As a result, there is great flexibility to change designs quickly, allowing fast time to market and even modifications during full production runs. EoPlex is a privately held company based in Redwood City, CA and is backed by ATA Ventures, Draper Fisher Jurvetson, Labrador Ventures and Draper-Richards. For more information, visit http://www.eoplex.com.
Abstract of Presentation by Arthur Chait for CPMT/SCV, February 13, 2008
A great deal of progress has been made in the field of nano and related "tiny" technologies. Unfortunately, the technology to link the tiny world to the macro world has not kept pace. The space between nano and macro is immense. At the nano end are self-assembling structures and semiconductor processes that deal in angstroms; and at the macro end are conventional machining and assembly techniques. Between these two extremes there is a gap where engineers struggle to make low-cost devices with complex 3-D structures containing multiple materials that are "Just Plain Miniature" (JPM).
This gap is often referred to as meso-scale and in this presentation we will consider a meso-scale of roughly 20 microns to 20 millimeters. A number of manufacturing technologies are used in this range including: thin film, lithography, etching, molding, embossing and micromachining. A very successful example is the application of semiconductor processing to create MEMs devices in silicon. MEMs airbag accelerometers and ink jet printer heads account for annual sales of several billion dollars per year.
However, semiconductor technology is not suitable for many other needs. Large, diverse markets exist for miniature devices that cannot be made with semiconductor technology and which require combinations of materials such as ceramics, metals and even polymers. The processes available to meet these needs are limited, costly and, in some cases, don't even exist. This presentation will review some of the existing technologies and then introduce a new technology call High Volume Print Forming (HVPF™) that is able to fill an important portion of this gap.
HVPF™ is an additive manufacturing process that deposits layers in large panels to produce thousands of individual parts. It has some similarities to semiconductor processing, since HVPF can utilize conductors and insulators in the same layer. For example, it can produce a ceramic package with buried passive components and circuit conductors all at the same time. The technology can build temporary elements from fugitive materials to produce channels and open structures after heat processing. It has some similarities to rapid prototyping (RP) in that it builds parts from layers, but unlike RP the process works with conductors, dielectrics, passive components and is an actual manufacturing process not a model making technique like RP.
HVPF™ can be utilized with special versions of screen, stencil, offset and litho printing. Other methods like micro-dispensers, tape casting and jet printing can also be used for certain design elements. All of these techniques require proprietary "inks" to produce the ceramic, metal, catalyst or polymer features. These inks must print to high tolerance, bond where required, set quickly during the build and then decompose to the final material such as metals or ceramics. At the same time, the thermal properties of the materials must be adjusted to accommodate shrinkage, thermal expansion and other parameters.
This talk will discuss the technology and describe applications including: cell phone antennas, energy harvesters to replace batteries, thermal management devices and microreactors for use in fuel cells.