Posted: April 23, 2008

SEMATECH's Litho Forum Spotlights High-Stakes Shift to Next-Generation Manufacturing

(Nanowerk News) The semiconductor industry’s movers and shakers will gather May 12–14 at SEMATECH’s bi-annual Litho Forum to debate how best to approach the high-stakes shift to 22 nm manufacturing.
“Lithography is a huge investment for manufacturers and suppliers alike. Where companies place their bets will have a big effect on their bottom line,” said Mike Lercel, director of SEMATECH’s lithography division and conference chair.
The forum will be keynoted by John Warlaumont, vice president of technology for SEMATECH. The agenda includes sessions organized by leading industry experts:
  • Extreme ultraviolet lithography – Janice Golda, director of lithography capital equipment development, Intel
  • 193 double patterning lithography – David Medeiros, senior manager of patterning research, IBM @ Albany Nanotech
  • 193 high index lithography – Will Conley, distinguished member of the technical staff, Technology Solutions Organization, Freescale Semiconductor
  • Nanoimprint lithography – Lloyd Litt, SEMATECH project manager, Alternative Lithography, Advanced Micro Devices
  • Maskless lithography – Burn Lin, senior director, Nanopatterning Technology, TSMC
  • Sessions will maximize discussion time, and attendees will be surveyed for their plans and preferences on lithographic approaches for future manufacturing. The survey will also assess how attendees perceive the development status of each option and its viability for the demands of large-scale manufacturing. Additional information is available at
    Lithography is a capital-intensive process. A single piece of next-generation lithographic equipment is expected to cost in excess of $40 million. The risk embraces manufacturers and suppliers alike. For any single technology or approach to be considered commercially viable, at least two equipment suppliers must support it.
    Lithography is a key process in the microfabrication of semiconductors. Light is used to transfer a geometric pattern from a photomask to a light-sensitive chemical photoresist on the substrate surface. A series of chemical treatments engraves the exposure pattern into the material underneath the photoresist. A CMOS wafer, for example, will go through the photolithographic cycle up to 50 times.
    SEMATECH works with members and partners on a pre-competitive basis to drive innovation from the lab through the manufacturing process. At the industry level, the organization plays a major role in arbitrating generational shifts by hosting industry-wide forums to foster dialogue and build consensus and helps maintain the International Technology Roadmap for Semiconductors (ITRS), a 15-year assessment of the industry’s future technology requirements.
    For 20 years, SEMATECH® (, the global consortium of leading semiconductor manufacturers, has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Today, we continue accelerating the next technology revolution with our nanoelectronics and emerging technology partners.


    Anne Englander, 512-356-7155

    [email protected]

    Source: Sematech
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