|Posted: Jul 23, 2014|
A*STAR and industry form S$200m Semiconductor R+D Joint Labs
|(Nanowerk News) Four joint laboratories, representing a commitment of S$200m between private and public sectors, were launched today between A*STAR's Institute of Microelectronics (IME), and its 10 industry partners. The Advanced Semiconductor Joint Labs will develop and advance semiconductor technologies for future electronics markets. The industry partners involved in this international collaboration are: Applied Materials, Dai Nippon Printing, DISCO, KLA-Tencor, Mentor Graphics, Nikon, Panasonic Factory Solutions Asia Pacific, PINK, Tokyo Electron Ltd. and Tokyo Ohka Kogyo.|
While expectations are for smart devices to sustain a compact form factor, consumers also expect powerful performance and low power consumption. The challenge for the semiconductor industry is to meet these needs by addressing system and integration scaling in the electronics market. The four joint labs in lithography, wafer level packaging (WLP), metrology and assembly, will provide an integrated platform for semiconductor R&D, starting with patterning, further development of 3D Integrated Circuits (IC), quality control, and finally, the assembly and high-volume manufacturing of chips.
The joint labs build upon the successful model of the IME-Applied Materials Centre of Excellence. Together, the four labs will enable the development of innovative semiconductor technologies and allow partners to undertake solutions-oriented semiconductor R&D and facilitate commercialisation that is earlier, faster and cheaper. This international partnership also bears testament to the industry relevance of IME's deep research capabilities, and will encourage further development of solutions for global implementation.
Mr Lim Chuan Poh, Chairman of A*STAR, said, "The launch of IME's Advanced Semiconductor Joint Labs today is an excellent example of public-private partnership under an open innovation framework. I am pleased that A*STAR IME has entered into this strategic partnership with many leading global industry players to capture new growth opportunities for Singapore and the region. The launch of the Advanced Semiconductor Joint Labs reaffirms A*STAR's deep capabilities and strong infrastructure in the R&D ecosystem to serve the growing needs of the semiconductor industry."
|Professor Dim-Lee Kwong, Executive Director of IME said, "These joint labs further demonstrate our ability to build a global network of partnerships that stretch across the supply chain. These collaborations will encourage semiconductor R&D that is relevant for industry, and provide solutions for a rapidly evolving global electronics market. Through this integrated platform, our partners can leverage A*STAR IME's technologies and expertise to develop innovative technologies and products to address challenges in the semiconductor industry."|
|About the Advanced Semiconductor Joint Labs|
|The Wafer Level Packaging Joint Lab|
|The Wafer Level Packaging (WLP) Joint Lab will focus on the development of advanced interconnect solutions and state-of-the-art equipment to bridge the increasing I/O interconnect gap between shrinking silicon geometries and printed circuit boards. The Joint Lab will develop innovative, and cost-effective interconnect solutions to enable logic and memory integration for low-power mobile devices and high-performance applications such as data centres. Cost-effective WLP solutions will be timely in catching the demand for wafer level packaging IC chips. According to Yole, in 2017, 23% of overall semiconductor IC wafers to be manufactured with packaging features are expected to be processed on wafer level scale.|
|Joint lab partners: Applied Materials, KLA-Tencor, Nikon and Tokyo Electron Ltd.|
|The Advanced Lithography Joint Lab|
|The Advanced Lithography Joint Lab seeks to develop advanced optical lithography technology used in the manufacturing of semiconductor chips. It will enhance capabilities for improving resolution, process window and control to mitigate device failure that is increasingly important due to chip shrinkage. In particular, it will focus on the development of lithography techniques such as direct self-assembly (DSA) and double/multiple patterning to facilitate scaling of ArF Deep Ultraviolet (DUV) dry and immersion down to 14nm and beyond, targeting advanced applications including logic, high density memory, embedded non-volatile memory, high-speed electronics and nanophotonics, and nano-electromechanical systems(NEMS).|
|Joint lab partners: Dai Nippon Printing, KLA-Tencor, Nikon, Mentor Graphics, Tokyo Ohka Kogyo and Tokyo Electron Ltd.|
|The Metrology Joint Lab|
|The Metrology Joint Lab will provide and develop necessary solutions in inspection and process controls to anchor developmental processes arising from the wafer level packaging and lithography joint labs. This will enable design and process optimization of integrated circuits for shrinking technology and cost-effective manufacturing solutions.|
|Joint lab partner: KLA-Tencor|
|The Assembly Joint Lab|
|The Assembly Joint Lab will focus on the development of bonding/de-bonding, fusion bonding, thermo-compression bonding and reflow bumping technologies to address existing issues such as high throughput and particle-free de-bonding, high throughput Chip on Wafer (CoW) for 2.5D/3D integration of ICs, and high-accuracy low-temperature wafer-level bonding. Tools and processes will be developed for high volume manufacturing of advanced multi-functional 2.5D and 3D ICs.|
|Joint lab partners: DISCO, Panasonic Factory Solutions Asia Pacific, PINK and Tokyo Electron Ltd.|
|1. This refers to the shrinking of both chips and chip packaging, while ensuring that more functions can be integrated onto a chip.|
|2. In semiconductor manufacturing, lithography is the patterning of microchips, and is considered a critical first step in ensuring chips are patterned robustly.|
|3. In 3D chip packaging, multiple chips can be stacked on top of each other and connected with wiring that runs vertically through the stack (called through-silicon vias or TSVs). This reduces package size, decreases power consumption and increases data bandwidth.|
|4. The Applied Materials and IME Centre of Excellence in Advanced Packaging was opened in 2012, and combines Applied Materials' leading-edge equipment and process technology with IME's leading research capability in 3D chip packaging.|
|5. Source: http://www.semi.org/eu/sites/semi.org/files/docs/5_Yole_Nanium%20Workshop.pdf|
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