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Posted: November 30, 2009
SEMATECH researchers to unveil next-generation device and process breakthroughs at IEDM
(Nanowerk News) Engineers from SEMATECH’s Front End Processes (FEP) program will present technical papers revealing research breakthroughs at the 55th annual IEEE International Electron Devices Meeting (IEDM) from December 7-9, 2009, at the Hilton in Baltimore, MD.
SEMATECH experts will report on low defect density high-k gate stacks for alternative III-V channel materials and non-planar devices, and discuss a new dry etch approach to minimize etch related leakage—a significant process technology advancement for next-generation logic and memory technologies.
“SEMATECH continues to make critical contributions to materials and process technology advancements for next-generation logic and memory devices. The industry is always looking for cost-effective technical solutions that are practical for manufacturing and SEMATECH’s front-end engineers are working to find new ways to extend CMOS in existing markets and to create opportunities for new emerging applications,” said Raj Jammy, SEMATECH’s vice president of materials and emerging technologies. “We are excited to share our research results with the technical community at the IEDM, which has always been a premier forum for sharing breakthrough developments in materials and process technologies for transistor and memory scaling.”
Additionally, SEMATECH will host an invitational pre-conference workshop entitled “Emerging Technologies in Solid State Devices” from December 5-6. The two-day workshop will focus on technical and manufacturing challenges affecting emerging memory technologies, energy-efficient devices, and III-V channel materials in CMOS devices. Co-sponsored by Tokyo Electron Limited and Aixtron AG, the workshop will feature experts from industry and academia debating the challenges and opportunities in these areas in a series of presentations and panel discussions.
During the IEDM conference, SEMATECH’s FEP experts will present research results at the following sessions:
Session 6, Monday, Dec. 7 at 2:25 p.m.: Impact of Dipole-Induced Dielectric Relaxation on High-frequency Performance in La-Incorporated HfSiON/Metal Gate nMOSFET – investigates the relationship of high frequency and dielectric relaxation of dipoles in La-doped HfSiON devices. This work was done in collaboration with POSTECH team from Korea.
Session 12, Tuesday, Dec. 8 at 11:10 a.m.: Dual Channel FinFETs as a Single High-k/Metal Gate Solution Beyond 22nm Node – shows that pFinFETs with a SiGe channel on insulator (SiGeOI) fabricated using standard CMOS processing exhibit 3.6X better hole mobility than silicon (100) while controlling the threshold voltage in single high-k and metal gate stacks.
Session 13, Tuesday, Dec. 8 at 10:45 a.m.: InGaAs MOSFET Performance and Reliability Improvement by Simultaneous Reduction of Oxide and Interface Charge in ALD (La)AlOx/ZrO2 Gate Stack – reports on the performance and reliability of ZrO2/In0.53Ga0.47As MOSFETs. An amorphous (La)AlOx interlayer at the ZrO2/In0.53Ga0.47As interface is key to reducing border and interface traps and moving the ZrO2 fixed charge away from the In0.53Ga0.47As.
Session 17, Tuesday, Dec. 8 at 3:35 p.m.: A Novel Damage-Free High-k Etch Technique Using Neutral Beam-Assisted Atomic Layer Etching (NBALE) for Sub-32nm Technology Node Low Power Metal Gate/High-k Dielectric CMOSFETs – demonstrates a novel damage-free neutral beam-based atomic etching process that successfully removes the residual high-k dielectric layer after gate patterning. This research was a collaborative effort with Sungkyunkwan University, Korea, and was partially supported by the National Program for Tera-Level Nano devices of the Korea Ministry of Science and Technology.
The IEDM Conference draws an international audience of industry professionals for an intensive exploration of design, manufacturing, physics, and modeling of semiconductors and other electronic devices. The conference spotlights leading work from the world’s top electronics scientists and engineers; it is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities, and other research institutions, many of whom are research partners.
For over 20 years, SEMATECH®, the global consortium of leading semiconductor manufacturers, has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Today, we continue accelerating the next technology revolution with our nanoelectronics and emerging technology partners.