Posted: April 19, 2010

Novel memristor chips for tomorrow's energy-efficient computers

(Nanowerk News) An innovative concept from scientists of the Jülich-Aachen Research Alliance (JARA) will pave the way for designing chips for future computers. For the generation after next of computer chips this development means higher computing power with significantly lower energy requirements - an important step for "green computing".
A working group headed by Professor Rainer Waser from Forschungszentrum Jülich and RWTH Aachen University has developed a novel switching concept and the related technology for so-called memristor chips. With their research findings, the scientists are preparing for a paradigm shift in the architecture of computer chips. The article presenting these findings is being published today in the internationally respected journal Nature Materials with the title "Complementary resistive switches for passive nanocrossbar memories".
It has been known for few years that memristor chips may play an important part in alternative architectures for future computers. Memristive cells have the special property that their resistance can be programmed (resistor) and subsequently remains stored (memory). However, it has so far not been possible to avoid a superimposition of information between adjacent cells in structured arrays when data is written onto such a structure – due to so-called sneak paths of the electrical current - without each cell being connected to its own transistor. The additional design effort involved limits the cell density of present arrays and consequently also their performance. Furthermore, it makes chip production much more expensive.
The research group achieved a breakthrough with respect to the fundamental problem of crosstalk between adjacent memristive cells. A member of Waser's group from RWTH Aachen University, Eike Linn, and his colleagues Roland Rosezin and Carsten Kügeler, both from Forschungszentrum Jülich, solved this challenge by developing a completely new switching concept. This concept is based on the antiserial switching of two memristive cells. Together, these cells form a novel unit, which the scientists termed a CRS cell (complementary resistive switch). No undesirable superimposition of information takes place between CRS cells.
Apart from avoiding the sneak paths, the passive arrays - fixed arrays of the new CRS cells - provide the advantage of particularly energy-efficient operation since such chip architecture can locally combine computing and memory areas. A large proportion of the energy required by today's computers arises from the classical von Neumann architecture, in which memory and computing areas are strictly segregated. The necessary data transport between the functional areas thus leads to high energy consumption.
With respect to performance, simulations show that in the technology of the next but one generation (transistor gate length 22 nanometres) arrays of the size of up to 108 (100 million) bits can be constructed using CRS cell arrays. In comparison, similar structures in present-day computers have a size of just 103 (thousand) bits on the lowest level and require a transistor for each cell in order to avoid the sneak path problem.
Source: Research Centre Jülich