Posted: May 22, 2008

International symposium on nanoscale architectures

(Nanowerk News) Moore's law based scaling is rapidly approaching a "brick wall" as we enter the nanoelectronic regime. Novel silicon and non-silicon nanoelectronic devices are being developed to explicitly address this problem. Similarly, while defect and fault-tolerance techniques are designed under the assumption that a system is composed largely of correctly functioning units, this is no longer true in emerging nanoelectronics. In addition, nanoelectronics offers massive parallelism on a scale significantly beyond anything we have seen before, yet very few commercial massively parallel applications are envisioned. Also, while current computer aided design tools and methodologies can barely manage billion-transistor chips, how can trillion-device chips that nanoelectronics promises be designed?
The purpose of the NANOARCH symposium on June 12-13, 2008 in Anaheim, CA, co-located with the 45th Design Automation Conference (DAC), is to be a forum for the presentation and discussion of novel architectures and design methodologies by considering these issues in future nanoscale implementations. The symposium seeks to build on the successes of NANOARCH in 2005, 2006 and2007. NANOARCH is interested in novel architectures including massively parallel, biologically inspired as well as those that are defect and fault tolerant, case studies on defect, fault and yield models, experimental reliability evaluation, validation frameworks, computer aided simulation, and design tools and emerging computational models for nanoelectronics. The symposium’s topics of interest include:
  • Architectures for nanoelectronic digital and mixed-signal circuits and systems
  • Computational paradigms and programming models for nanoscale architectures
  • Modeling and simulation of nanoelectronic devices, circuits and system architecture
  • Simulation of complex systems with nanoscale computing architectures
  • Implementing microarchitecture concepts using nanoarchitecture building blocks
  • Defect and fault tolerant nanoelectronic device, circuit, and system level architectures
  • Manufacture testing of nanoelectronic architectures
  • Computer aided design tools and methodologies for nanoelectronic architectures
  • In addition to technical and invited sessions, the program will include two keynote speakers and a panel discussion, each open to all DAC participants. Information on the panel and keynote talks:
    Keynote Talk (Open to all DAC attendees) Speaker: Dr. R. Stanley Williams, HP Labs, Palo Alto, CA Thursday, June 12 11:00am – 12:00pm
    Panel Session (Open to all DAC attendees) Non-CMOS NanoElectronics - Will it ever be real? Thursday, June 12 4:00pm – 5:30pm Organizer/Moderator: Dr. Paul D. Franzon, N.C. State, Raleigh, NC
    Keynote Talk (Open to all DAC attendees) Speaker: Dr. James R. Heath, California Institute of Technology, Pasadena, CA Friday, June 13 11:00am – 12:00pm
    The two day symposium will also include several technical sessions on topics such as reliable nanoarchitectures, CAD for nanoelectronic devices and circuits, defect tolerant memories and circuits, and nanoelectronic circuits.
    More information:
    Source: IEEE
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