The latest news from academia, regulators
research labs and other things of interest
Posted: January 26, 2010
European research project DIAMOND launched - goal is to reduce semiconductor verification costs
(Nanowerk News) European research project DIAMOND - Diagnosis, Error Modelling and Correction for Reliable Systems Design - was launched in January 2010. With the total budget of 3.8M Euro the project encompasses an effort of 462.5 person months over a period of 3 years. Under the lead of Prof. Roderick Bloem, IAIK will contribute to this project with a budget of more than half a million Euros.
Increasing verification costs are a major challenge facing the semiconductor community. While diagnosis and correction of errors are more time-consuming compared to error detection, they have received far less attention, both, in terms of research works and industrial tools introduced. Another, orthogonal, threat to the development is the rapidly growing rate of soft errors in the emerging nanometer technologies. However, the design community is not ready for this challenge as the existing soft error escape identification methods for sequential logic are inadequate.
The aim of DIAMOND is improving the productivity and reliability of semiconductor and electronic systems design in Europe by providing a systematic methodology and an integrated environment for the diagnosis and correction of errors. The project will develop:
A holistic diagnostic model for design and physical errors (e.g. soft errors, defects etc.);
Automated location and correction techniques based on the unified model, both pre-silicon and post-silicon;
Implementation of a reasoning framework for location and correction, encompassing word-level techniques, formal, semi-formal, and dynamic techniques;
Integration of automated correction with the diagnosis methods.
DIAMOND reaches beyond the state-of-the-art by proposing an integrated approach to location and correction of specification, implementation, and soft errors. In addition, it considers faults on all abstraction levels, from specification through implementation down to the silicon layout. Handling this full chain of levels allows DIAMOND take advantage of hierarchical diagnosis and correction capabilities incorporating a wide range of error sources.
DIAMOND research will enhance the chip system-level standards by proposing diagnostic modeling libraries, which would integrate into the layered library structure of the Open SystemC Initiative (OSCI). At the board-system level the project is expected to build on the emerging standards of IJTAG and SJTAG for the purpose of in-situ diagnosis and repair.
About the consortium
DIAMOND project brings together eight partners: two major corporations IBM Israel and Ericsson AB (Sweden), two EDA companies TransEDA Systems (Hungary) and Testonica Lab (Estonia); and four Universities: Universität Bremen (Germany), Graz University of Technology (Austria), Linköping University (Sweden), and Tallinn University of Technology (Estonia).
The profiles of DIAMOND partners cover a sufficiently wide spectrum of competences required to guarantee a successful completion of the project. The main responsibility field of Universität Bremen is in automated reasoning engines. The team has a high level of competence in, both, debugging design and implementation errors and analysis of soft error resilience. Linköping University, whose Department of Computer and Information Science is one of the largest for in Northern Europe focuses on error analysis and in-situ diagnosis techniques. The IAIK will use its considerable expertise in formal verification, design error location and correction methods.
IBM Israel is one of the end users and in addition to validating the DIAMOND’s flow, its main responsibility is in formal and dynamic assertion-based verification and identifying soft error escapes. Ericsson is the world’s leading provider of technology and services to telecom operators having a great experience in participating in European cooperative research projects. TransEDA is the leader in Verification Closure Measurement solutions for electronic designs. Testonica Lab’s competence embraces electronic systems debug and test tools, which will be supplied with post-silicon and in-situ diagnostic access capabilities based on IJTAG/SJTAG emerging standards. All the end users will be exploited for testing and assessing the methodologies developed in DIAMOND. Administrative capacity for the implementation of the project is ensured by Tallinn University of Technology.
Source: Technical University Graz
If you liked this article, please give it a quick review on reddit or StumbleUpon. Thanks!