The latest news from academia, regulators
research labs and other things of interest
Posted: March 1, 2010
European TRAMS project designs the memory for future nanoscale processors
(Nanowerk News) The TRAMS project aims to guarantee that the memory for future nanoscale processors, with teraflop capacity, is resilient, reliable, fault tolerant, and energy efficient, with advanced features.
The Universitat Politècnica de Catalunya (UPC-Barcelona Tech) leads a European project to design memory for the computers of the future. The Terascale Reliable Adaptive Memory Systems (TRAMS) initiative is a Future Emerging Technologies (FET) collaborative research project approved by the European Commission as part of the Seventh Framework Program for Research and Technological Development. In addition to the UPC-Barcelona Tech, the universities and companies participating in the project are the IMEC nanotechnology research center, the University of Glasgow and Intel Corporation Iberia.
It is expected that in the coming decade, as a result of the continuing miniaturization of transistors and consequent performance improvements described by Moore's law (devised by Gordon Moore, founder of Intel Corporation), a single chip will be able to perform trillions of operations per second, providing a bandwidth of several trillion bytes per second. These incredible computing capacities will not only dramatically increase the processing throughput of large data centers and computing services, but also the potential consumers and the functionality of personal computers, communications devices, and all electronic entertainment products and domestic appliances.
However, nanoscale transistor devices that incorporate the new computer processors will be very susceptible to manufacturing faults, with unprecedented variability and, in general, low operational reliability. The TRAMS project aims to help guarantee reliable, energy-efficient computing systems with advanced computing features. It will research new memory systems for nanoscale processors with teraflop capacity, that is, the capacity to perform trillions of operations per second.
Guaranteeing advanced technologies
The project focuses on research into the technology of cutting-edge devices, transistors, circuits and integrated systems, i.e. the systems that the International Technology Roadmap for Semiconductors (ITRS) includes as technological challenges, as well as any new technologies that may follow them.
The starting point will be the latest Complementary Metal Oxide Semiconductor (CMOS) technologies, which are the most commonly used in the manufacture of integrated circuits in most electronic products. The project includes the study of the new generations of chips with transistor sizes below 16 nm (whereas the current ones are 32 nm), as well as architectures with advanced devices (multigate devices, which are controlled from two or more different electrodes). It will also study new gate and channel materials that are being designed with a scale of less than 10 nm (they can be as small as 6 nm).
In addition, the project will also analyze emerging technologies, such as nanowire transistors, quantum devices, carbon nanotubes, graphene and molecular electronics, which are expected to reach sizes of less than 5 nm.
All of this new technology promises an increase in the density of integration of components, as well as performance and functionality, to hundreds of times the current values. However, at this scale, a dramatic reduction in the quality and reliability of components is also expected, with intense degradation effects, a sharp reduction in the signal to noise ratio and extreme variability of characteristics. Thus it is necessary to research new techniques and design rules for circuits and systems to guarantee reliable and robust systems in spite of the reduced quality of the components. To enable reliable, robust, fault and defect tolerant nanoscale memory systems to be built at a reasonable cost and with less designer effort, the TRAMS project will study these new devices, define new design paradigms and implement principles of hierarchical design.