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Posted: Apr 17, 2013
Study says 20nm SRAM design could suffer from the interplay between statistical variability and reliability
(Nanowerk News) Gold Standard Simulations (GSS) revealed that the interplay between the effects of statistical reliability and variability could adversely affect 20nm CMOS SRAM yield. The study also defined a new reliability simulation framework to predict variability and reliability impact that enhances yield.
The findings were presented in a paper jointly authored by GSS and the University of Glasgow Device Modelling Group at the International Physics Reliability Symposium in Monterey, CA.
The research highlights the importance of the interaction between trapped charges and statistical variability in the prediction of transistor and circuit lifetimes. It also describes the development of a unique simulation framework and a set of validated tools that could greatly enhance design and yield predictions in advanced technologies.
According to the study, the interplay amongst individual trapped charges with random discrete dopants (RDD), line edge roughness (LER) and metal gate granularity (MGG) in 20nm CMOS transistors leads to wide dispersions in transistors characteristics and to gigantic random telegraph noise (RTN) amplitudes that adversely affect SRAM yield and reliability. Even a single trapped electron can disturb the information stored in an SRAM memory cell.
The new simulation framework introduced today links atomistic-scale transistor reliability simulations and circuit level SRAM simulations that focus on the interaction of individual trapped charges with key transistor variability sources.
A newly-developed Kinetic Monte Carlo (KMC) reliability simulation engine, embedded in the GSS GARAND 3D 'atomistic' simulator, enables seamless statistical simulation of Bias Temperature Instability (BTI), Random Telegraph Noise (RTN) and Trap-Assisted Tunneling (TAT), all of which critically affect contemporary and future SRAM reliability and yield.
The new KMC engine handles the dynamics of random charge trapping and de-trapping in GARAND's drift-diffusion simulation engine. This allows accurate physical modelling of the time evolution of bias and temperature-dependent transistor degradation statistics.
The results are then transferred into highly accurate time-dependant statistical compact models (using the GSS statistical compact model extractor Mystic). The GSS RandomSpice statistical circuit simulation engine captures the impact of statistical reliability on SRAM behaviour. This highly accurate process allows reliability-enhancing countermeasures to be implemented during the SRAM design process.
"The idea behind the research is not only to be able to predict failure times, but also to increase them. Hence the need for a new reliability simulation framework capable of transferring predictive atomistic simulations up to the circuit level in order to improve device and circuit reliability," explained Dr. Asen Asenov, CEO Gold Standard Simulations.
About Gold Standard Simulations
Gold Standard Simulations is the world leader in simulation of statistical variability in nano-CMOS devices. The company's services include the physical simulation of statistical variability, statistical compact model extraction and statistical circuit simulation using "push button" cluster-based technology. For more information please visit http://www.GoldStandardSimulations.com.
Source: Gold Standard Simulations
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