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Posted: Mar 11, 2014
Metallurgical challenges in microelectronic 3D IC packaging technology
(Nanowerk News) Mobile hand-held consumer electronic products have a rapid growing market today, witnessed by the popularity of Apple products.
Most people make their first contact to internet, not by a PC, rather by a smart phone. The phone is no longer a phone, but it provides various functions for communication and for entertainment. Not only we can have recorded information such as books, images, songs, and movies from the phone or i-pad, but also we can have instant information such as traffic jam when we drive home, as well as breaking news at the last moment. It is expected that very soon when we hold our cell phone, it will detect our body temperature, heart pulse, and blood pressure. The vital signals of our body can be recorded every day and an abnormal signal can be detected when it is compared instantaneously to the personal record in the cell phone. Indeed, it seems that the functions we can have in the future hand-held devices are only limited by our imagination.
This is a challenge to microelectronic industry because it is more of a problem in packaging technology rather than in chip technology, since as the bridge between Si chips and human interfaces of hand held devices, we cannot bypass packaging technology. Today, 2-dimensional very-large-scale-integration of transistor circuits on a silicon chip has more or less reached the limit of Moore's law and the industry has been looking for ways to extent the limit. The way that seems most promising now is to use 3D IC in which several semiconductor chips are stacking together. A very good reason to do so is that it saves space in a device having a tight requirement of space. The stacking requires vertical wiring to connect the chips electrically. Microelectronic companies are developing Through-Si-Vias (TSV) technology and microbump (solder) technology for the vertical interconnections.
In packaging technology, microelectronic industry has had experience in packaging flip chip devices for a long time, which has been applied to manufacturing mainframe computers as well as consumer electronic products. The evolution from flip chip to 3D IC technology is because while chip technology is limited by Moore's law, packaging technology has no Moore's law yet, so it has amble room for miniaturization. When chip technology is combined with packaging technology, the future growth of electronic industry for 15 to 20 years seems certain. We can illustrate the prediction by using the size of solder joints. The solder joints in flip chip technology are about 100 µm in diameter. For microbumps in 3d IC technology, it is about 20 to 10 µm in diameter. We should be able to reduce the diameter to 1 µm, and it may take 15 to 20 years to do so. This is because the reduction is not without obstacles. For example below:
When the solder joint diameter is reduced 10 times, from 100 to 10 µm, the volume is reduced by 1000 times. It has a very big effect on microstructure homogeneity. This is because if we assume the grain size in the solder joint is 10 µm in diameter, the microbump will have one grain, yet the flip chip will have 1000 grains. In the latter, we can assume the joint to be isotropic because of a large number of randomly oriented grains, but not in the former where we will have anisotropic properties. This is undesirable from the point of view of early failure in reliability. Another case is joule heating, which is most likely the most serious reliability issue. How to conduct the heat away in the 3D IC device will be a challenge. To conduct heat, we must have temperature gradient. If we assume a temperature difference of 1 °C across a microbump of 10 µm in diameter, the temperature gradient is 1000 °C/cm, which is very large in heat transfer. We can exceed it easily in 3D IC devices.