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Posted: Apr 19, 2011

Free webinar: Taming Extreme Topography for Microelctronics Applications

(Nanowerk News) Join a panel of experts on Wednesday, April 27, 2011 at 8:00 AM PDT to learn about the next generation of planarizing materials to solve your high-aspect-ratio challenges.
Advance registration is required: please click here.
Fabrication of microelectronic devices increasingly involves the creation of high-aspect-ratio structures, that is, those with large height or depth to narrow width, such as trenches, vias, columns, and mesas. These structures provide isolation; serve as conduits for electrical, optical, or fluid signals; or enable pre-dicing before die singulation. New designs in semiconductor and MEMS devices are pushing the aspect ratios to the 10:1 range.
For semiconductors, these designs may take the form of trenches 600 nm deep and 60 nm wide. For MEMS, these may be vias 500 Ám deep and 50 Ám in diameter. After these structures are created, additional photolithographic processing of the wafers is necessary. The technology to create these high-aspect-ratio structures, however, has outpaced the ability of existing technologies to process photoresists over them. This disparity has created a demand for materials that can level the surface of these processed wafers so that subsequent conventional photolithography processes can be used.
Brewer Science is applying its 30 years of experience in developing and providing innovative spin-applied coatings that enhance photolithography to create such materials. We are creating a series of self-leveling coatings that are compatible with existing lithography processes and photo resists, allow processing over extreme topography, and are easily removed. These materials will expand engineering design capabilities, increase a device's value, and minimize production costs.
Source: Brewer Science
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