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Posted: Aug 22, 2011
New technique for trench narrowing and via filling with selective SiGe deposition
(Nanowerk News) Imec has developed a new method for the preferential deposition of silicon-germanium (SiGe) through chemical vapor deposition (CVD). They have further engineered this method into an innovative technique for trench narrowing and via filling through deposition only, i.e. without the need of litho/etch and subsequent chemical mechanical polishing (CMP). This technique offers a path to decreasing the number of process operations and thus reducing IC manufacturing costs.
SiGe Deposition: Preferentially deposited CVD SiGe for trench narrowing.
Integrating functional modules of heterogeneous nature (e.g., analog CMOS or MEMS) may require deep trenches with high aspect ratios. These are typically made with the help of photolithography and plasma etch processing. Narrowing these trenches is typically done by filling them with a material and then selectively etching the filling material away to achieve the desired trench width. But this technique requires expensive and complex photolithography and plasma etch processing.
As for vias, the conventional filling techniques at interconnect level require an additional CMP step for surface planarization. These additional etching and planarization processes are complex, add defects that reduce the yield, and are thus costly. So finding alternative methods that do not require complex photolithography and etch for trench narrowing and CMP processing for via filling is a possible way of reducing the number of manufacturing process operations, and thus the manufacturing costs.
Imec has recently invented a novel method for preferentially depositing boron-doped SiGe with CVD. The preferential deposition is achieved by pre-treating the substrates with a CF4 RF-plasma, which increases the coalescence time of SiGe deposition on SiO2 substrates, compared to SiGe substrates. The coalescence time is the time that it takes before a nucleation layer is fully formed on the substrate surface and continuous SiGe deposition begins.
This effect is due to the addition of C and F to the SiO2 substrate, which greatly reduces the surface density of the crystalline grains formed during the incubation period. The CF4 pre-treatment and CVD deposition can be performed either sequentially in the same processing chamber without a vacuum break, or separately in different processing chambers or equipment.
We have used this method to engineer deposition-only techniques for trench narrowing and via filling. These simplified techniques require fewer expensive and complex processing operations. We have successfully demonstrated the feasibility of these techniques. Adopting them will result in less complex processes than conventional methods of trench narrowing and via filling. This will offer IC manufacturers potential cost and cycle time improvements by reducing the number of processing operations.