| Oct 14, 2025 |
Researchers chart roadmap to unlock next-gen 2D transistor technology
Researchers unveil a roadmap for 2D transistor gate stack design, marking a key step toward ultra-efficient chips that could replace silicon technology.
(Nanowerk News) A team at Seoul National University (SNU) has drawn up a detailed roadmap for advancing “gate stack” technology — the key to unlocking the full potential of next-generation two-dimensional (2D) transistors. The study, led by Professor Chul-Ho Lee from the Department of Electrical and Computer Engineering, was published in Nature Electronics ("Gate stack engineering of two-dimensional transistors").
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For decades, silicon-based CMOS technology has powered ever-smaller, faster, and more efficient chips. But as these devices shrink below the nanometer scale, silicon’s physical limits are becoming a roadblock. That’s where 2D semiconductors come in. These atomically thin materials can maintain their performance even at extreme scales, making them prime candidates for the post-silicon era.
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Major chipmakers including Samsung, TSMC, Intel, and IMEC are already investing heavily in 2D transistor research, with plans to bring the technology to market after the mid-2030s. What was once a distant vision is now a fast-approaching reality in semiconductor development.
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Yet one critical challenge remains: integrating the “gate stack,” a layered structure that controls a transistor’s current flow. Existing silicon processes don’t work well with 2D materials. They often damage the insulating dielectric layer, create defects, and cause current leakage — all of which limit performance.
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Professor Lee’s team tackled this issue head-on. Their study systematically analyzed five different gate stack integration methods — including van der Waals (vdW) dielectrics and their variations — and evaluated each approach based on factors such as interface quality, oxide thickness, and gate leakage. The results were benchmarked against targets set by the International Roadmap for Devices and Systems (IRDS), producing a clear guide for both researchers and industry engineers.
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The team also explored the promise of ferroelectric materials in gate stacks. These materials retain electric polarization without external power, opening the door to ultra-low-power logic, non-volatile memory, and in-memory computing. The study emphasized real-world readiness, outlining requirements such as low-temperature processing below 400°C, wafer-scale uniformity, and long-term reliability — all vital for semiconductor manufacturing.
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“This research presents a standard blueprint to overcome the biggest challenge in commercializing 2D transistors — achieving high-quality gate stacks,” said Professor Lee. “It offers both academic insight and industrial guidance. We plan to expand this work through collaboration with industry partners.”
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The roadmap offers a quantitative foundation for developing 2D transistors that could power future AI chips, ultra-efficient mobile devices, and high-density servers. Beyond advancing theory, the SNU team is shaping the practical technologies needed to bring 2D semiconductors from the lab to the factory floor.
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Dr. Yeon Ho Kim, the paper’s first author and a postdoctoral researcher at SNU, continues to work on contact and gate stack engineering for 2D transistors. Building on this study, he’s expected to play a key role in the next wave of semiconductor innovation.
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