SEMATECH announces breakthroughs in controlling parasitic contact resistance in advanced CMOS devices
Posted: June 15, 2009

SEMATECH announces breakthroughs in controlling parasitic contact resistance in advanced CMOS devices
(Nanowerk News) SEMATECH’s continued leadership in developing, screening, and characterizing new materials, tools, and processes that enable CMOS scaling and emerging technologies will be further demonstrated during the 2009 VLSI Technology Symposium on June 15–17, 2009, at the Rihga Royal Hotel in Kyoto, Japan.
In one area of investigation, technologists from SEMATECH’s Materials and Emerging Technologies program have demonstrated significant reductions in Schottky barrier height and contact resistance that are critical for continued enhancement of device performance in future technology nodes.
As scaling continues, one of the most pressing concerns of CMOS technology beyond the 45 nm node is the contact resistance in source/drain regions, which comes from a relatively high Schottky barrier between n-type doped Si and nickel silicide. SEMATECH researchers will outline recent progress in exploring alternative interface structures, reducing the parasitic resistances of the source and drain regions and improving mobility.
“Through intense research and development efforts, SEMATECH has developed manufacturable solutions with new materials and interfaces that reduce source-drain parasitic resistance. These practical implementation approaches enable future advanced gate and high-mobility channels,” said Raj Jammy, SEMATECH’s vice president of emerging technologies. “We’re continuing to push CMOS technology to the limits, while we test the feasibility of emerging next-generation technologies.”
SEMATECH driven advancements in materials and device structure will be highlighted at the symposium, including the following:
  • A newly offered focus session, “3D-System Integration,” SEMATECH’s director of 3D interconnect program, Sitaram Arkalgud, will deliver an invited talk highlighting the importance of 3D TSV integration for future technology generations.
  • An expert panel discussion, “Key Technology Options for 16 nm CMOS and Beyond – Breaking the Barriers” will include SEMATECH’s Raj Jammy.
  • The panel “Is TSV 3D LSI’s and Packaging Finally Ready or Is It Just Another Fantasy?,” co-moderated by Sitaram Arkalgud, will address the question of which applications are driving the development of TSVs.
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    Additionally, experts from SEMATECH’s Materials and Emerging Technologies program will present six technical papers:
  • Gate First High-k/Metal Gate Stacks with Zero SiOx Interface Achieving EOT=0.59nm for 16nm Application – Demonstrates for the first time a HfOx films with a zero low-k SiOx interface has better scalability than exotic higher-k materials, and is a practical, scalable option for today’s industry-standard Hf-based high-k films.
  • Vth Variation and Strain Control of High Ge% Thin SiGe Channels by Millisecond Anneal Realizing High Performance pMOSFET Beyond 16nm Node – Explores key parameters for controlling threshold voltage variation and strain maintenance of gate first SiGe channel pMOSFETs.
  • Selective Phase Modulation of NiSi Using N-Ion Implantation for High Performance Dopant- Segregated Source/Drain n-Channel MOSFETs – Investigates dual phase-modulated Ni silicide for reducing the Schottky barrier and series resistance in dopant-segregated source/drain nMOSFETs.
  • CMOS Band-Edge Schottky Barrier Heights Using Dielectric-Dipole Mitigated (DDM) Metal/Si for Source/Drain Contact Resistance Reduction – Demonstrates for the first time Schottky barrier height tuning using interfacial SiO2 and dual high-k dielectrics.
  • A Scalable and Highly Manufacturable Single Metal Gate/High-k CMOS Integration for Sub-32nm Technology for LSTP Applications – Outlines a simple, scalable gate-first integration option for manufacturing high-k metal gate CMOS transistors targeted for sub-32nm low standby power applications.
  • Mechanisms for Low On-State Current of Ge (SiGe) nMOSFETs: A Comparative Study on Gate Stack, Resistance, and Orientation-Dependent Effective Masses – Reports the results of a systematic study to understand the low drive currents observed in Ge-based nMOSFETs.
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    The International Symposium on VLSI Technology, Technology and Circuits is sponsored by the IEEE Electron Devices and Solid-State Circuits societies and the Japan Society of Applied Physics in cooperation with the Institute of Electronics, Information and Communication Engineers. VLSI Japan is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities, and other research institutions, many of whom are research partners.
    About SEMATECH
    For over 20 years, SEMATECH®, the global consortium of leading semiconductor manufacturers, has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Today, we continue accelerating the next technology revolution with our nanoelectronics and emerging technology partners.
    Source: SEMATECH
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