| Jun 23, 2025 |
Terahertz method maps silicon chip interiors without cutting or contact
A new terahertz technique reveals nanometer-scale PN junction depths in silicon chips, enabling faster, non-contact inspection for advanced semiconductor manufacturing.
(Nanowerk News) Silicon large-scale integrated (LSI) circuit manufacturing is essential to modern life. However, until now, there has been no wafer-scale technology that allows quick, non-destructive, and non-contact inspection of the inner electric field, how electric carriers move, where defects are, and how fast devices respond. This has become more important as electronic devices are getting smaller and more complex, with 3D structures to increase how much they can hold and process.
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In a new study published in Light: Science & Applications ("Non-contact and nanometer-scale measurement of PN junction depth buried in Si wafers using terahertz emission spectroscopy"), a team of scientists from Okayama University, Rice University, the Samsung Japan Research Institute Group, and the Samsung Electronics Group, led by Professor Masayoshi Tonouchi from the Research Institute for Interdisciplinary Science at Okayama University in Japan, has created a new method. This method can measure how deep a PN junction is inside a silicon wafer—without touching or damaging it—and with nanometer-level accuracy. This is the first time this has been achieved in such a way.
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The PN junction inside the silicon wafer is hit with an extremely fast laser pulse called a femtosecond laser. When this laser shines on the junction, it creates a type of wave called a terahertz (THz) electromagnetic wave. This happens because the laser generates electric carriers (electrons and holes) at the PN junction.
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As shown in the researchers’ figure, these carriers are pushed by the electric field in the depletion region: electrons go toward the n-type silicon layer, and holes go toward the p-type layer. This sudden movement of charges creates an electric current, which then produces the terahertz waves. These THz waves travel to the surface of the wafer and are emitted into the air.
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| a Schematic illustration of the buried channel transistor structure. b THz emission from the PN junction. Ultrafast photocarrier transport due to the built-in electric field (drift current) generates the THz electromagnetic waves at the PN junction. c PN junction depth dependence of the THz emission. A, B, and C represent the energy band diagram in Si wafers with different PN junction depths. Photocarrier density at PN junctions depends on their depth. Consequently, the amplitude of the THz emission from the PN junctions is sensitive to the depth. (Image: Light: Science & Applications, CC BY)
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Professor Tonouchi explained that although the behavior of the photocarriers that generate the THz waves is very fast and complex, it can be understood more simply by using a basic model. With this model, it becomes easier to see how the carriers move and to estimate how deep the PN junction lies inside the wafer. This research introduces, for the first time, a step-by-step method to estimate that depth using the THz waves produced at the junction.
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Dr. Murakami, a young researcher on the team, pointed out that one of the challenges was using a laser with a short enough wavelength to excite the shallow PN junctions in silicon. Normally, the standard femtosecond laser has a wavelength of around 800 nanometers, which means it goes deeper than 10 micrometers into silicon. This makes it unsuitable for detecting shallow junctions. But they discovered that using a laser with about half that wavelength works better in this case. By adjusting the wavelength, they were able to measure even shallower junctions more accurately.
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As semiconductor devices become more advanced and packed with even more components, the need for better testing methods is growing. This new technology allows quick, non-contact, and non-destructive inspection of what’s happening inside a silicon wafer—something that was hard to do with earlier tools. The researchers believe this could lead to not only better testing of wafer structures, but also a full measurement system that could be used during the chip manufacturing process itself. That would help make devices more reliable while also reducing the materials and energy used during production.
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