Jun 02, 2026

Spintronics p-computer ready for scale-up

Researchers used state-of-the-art semiconductor fabrication technologies to demonstrate how we could be ready for large-scale spintronic p-computers.

(Nanowerk News) A Japan-U.S. collaborative research team has demonstrated the world's first integrated spintronic probabilistic bit (p-bit) fabricated on a silicon chip using semiconductor manufacturing processes. The team, consisting of researchers from Tohoku University and the National Institute of Standards and Technology, experimentally verified the operation of the p-bit, a key building block for probabilistic (p-) computers. The achievement provides a pathway toward large-scale spintronic p-computers for applications such as AI and machine learning.

Many emerging computational problems require efficient exploration of enormous numbers of possible states. Conventional computers, which process binary information (0 or 1) sequentially, are not always well suited to such highly parallel tasks. Probabilistic computers instead use probabilistic bits, or p-bits, which fluctuate stochastically between 0 and 1 by utilizing intrinsic physical randomness.

Because p-computers can quickly take many states, they are attracting attention as a next-generation computing platform. Among several candidate technologies, spintronics is considered especially promising because nanoscale magnetic devices can naturally generate probabilistic behavior through magnetic fluctuations.

In this work, Drs. Ju-Young Yoon, Nuno Cacoilo, Shun Kanai, Shunsuke Fukami, William Andrew Borders, and other collaborators fabricated spintronic p-bits directly on a silicon chip by combining state-of-the-art semiconductor fabrication technologies in Japan and the United States. Transistors and lower interconnect layers were first fabricated using the 130-nm CMOS process provided by SkyWater Technology. Superparamagnetic nanodevices and upper electrodes were then integrated using spintronic device fabrication facilities at Tohoku University.

(a) Photograph of test chips fabricated on a silicon substrate using semiconductor integrated circuit manufacturing processes. (b) Schematic cross-sectional structure of the spintronic p-bit. Transistors and lower interconnect layers were fabricated at SkyWater Technology, followed by fabrication of the spintronic devices at the Research Institute of Electrical Communication, Tohoku University. (c,d) Cross-sectional and plan-view electron microscope images of the spintronic device designed to exhibit stochastic fluctuations. (Image: Tohoku University)

The researchers confirmed two essential characteristics of p-bit operation: stochastic fluctuations of the output voltage over time, and controllability of the time-averaged output through an input voltage. This is the world's first demonstration of a spintronic p-bit monolithically fabricated on a silicon chip using semiconductor integrated circuit processes.

The result opens a path toward scaling spintronic p-computers far beyond current manually assembled prototypes. By further advancing device and circuit technologies and increasing the number of integrated p-bits, the researchers expect spintronic p-computers to move closer to large-scale practical implementation.

The findings were published in IEEE Electron Device Letters ("130-nm CMOS-integrated superparamagnetic tunnel junction-based p-bit").

This work was made possible by the NIST-led Nanotechnology Xccelerator program that distributes open-source circuit designs for integration of novel technologies on CMOS.

Source: Tohoku University (Note: Content may be edited for style and length)